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CDP1881CE

Description
1800 SERIES, HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP20
Categorysemiconductor    logic   
File Size51KB,8 Pages
ManufacturerIntersil ( Renesas )
Websitehttp://www.intersil.com/cda/home/
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CDP1881CE Overview

1800 SERIES, HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP20

CDP1881C,
CDP1882, CDP1882C
March 1997
CMOS 6-Bit Latch
and Decoder Memory Interfaces
Description
The CDP1881C, CDP1882 and CDP1882C are CMOS 6-bit
memory latch and decoder circuits intended for use in
CDP1800 series microprocessor systems. They can inter-
face directly with the multiplexed address bus of this system
at maximum clock frequency, and up to four 4K x 8-bit mem-
ories to provide a 16K byte memory system. With four 2K x
8-bit memories an 8K byte system can be decoded.
The devices are also compatible with non-multiplexed
address bus microprocessors. By connecting the clock input
to V
DD
, the latches are in the data-following mode and the
decoded outputs can be used in general purpose memory-
system applications.
The CDP1881C, CDP1882 and CDP1882C are intended for
use with 2K or 4K byte RAMs and are identical except that in
the CDP1882 MWR and MRD are excluded.
The CDP1882 is functionally identical to the CDP1882C. It
differs in that the CDP1882 has recommended operating
voltage range of 4V to 10.5V and the C version has a recom-
mended operating voltage range of 4V to 6.5V.
The CDP1881C, CDP1882 and CDP1882C are supplied in
20 lead and 18 lead packages, respectively. The
CDP1881C is supplied only in a dual-in-line plastic pack-
age (E suffix). The CDP1882 is supplied in dual-in-line,
hermetic side-brazed ceramic (D suffix) and in plastic (E
suffix) packages.
Features
• Performs Memory Address Latch and Decoder
Functions Multiplexed or Non-Multiplexed
• Decodes Up to 16K Bytes of Memory
• Interfaces Directly with CDP1800-Series Microproces-
sors at Maximum Clock Frequency
• Can Replace CDP1866 and CDP1867 (Upward Speed
and Function Capability)
Ordering Information
TEMP.
RANGE
(
o
C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PKG.
NO.
E20.3
E18.3
E18.3
D18.3
PACKAGE
PDIP
PDIP
PDIP
Burn-In
SBDIP
5V
CDP1881CE
CDP1882CE
CDP1882CEX
-
10V
-
-
-
CDP1882D
Pinouts
CDP1881C
(PDIP)
TOP VIEW
CDP1882, CDP1882C
(PDIP, CERDIP)
TOP VIEW
CLOCK
MA5
MA4
MA3
MA2
MA1
MA0
MRD
MWR
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
A8
A9
A10
A11
CS0
CS1
CS2
CS3
CE
CLOCK
MA5
MA4
MA3
MA2
MA1
MA0
CE
V
SS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
V
DD
A8
A9
A10
A11
CS0
CS1
CS2
CS3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
1367.2
4-1

CDP1881CE Related Products

CDP1881CE CDP1881C CDP1882 CDP1882C CDP1882CE CDP1882D CDP1882CEX
Description 1800 SERIES, HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP20 1800 SERIES, HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP20 1800 SERIES, HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP20 1800 SERIES, HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP20 1800 SERIES, HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP18 HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP18 1800 SERIES, HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP18

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