ICS8705BYLFT datasheet, PDF - EEWORLD Datasheet

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ICS8705BYLFT: DescriptionZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR; File Size286KB，17 Pages; ManufacturerICS ( IDT ); Websitehttp://www.icst.com

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ICS8705BYLFT Overview

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

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Integrated

Circuit

Systems, Inc.

ICS8705

ERO

ELAY

, D

IFFERENTIAL

-LVCMOS/LVTTL

LOCK

ENERATOR

EATURES

• 8 LVCMOS/LVTTL outputs, 7Ω typical output impedance

• Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs

• CLK1, nCLK1 pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

• CLK0 input accepts LVCMOS or LVTTL input levels

• Output frequency range: 15.625MHz to 250MHz

• Input frequency range: 15.625MHz to 250MHz

• VCO range: 250MHz to 500MHz

• External feedback for “zero delay” clock regeneration

with configurable frequencies

• Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• Fully integrated PLL

• Cycle-to-cycle jitter: 45ps (maximum)

• Output skew: CLK0, 65ps (maximum)

CLK1, nCLK1, 55ps (maximum)

• Static Phase Offset: 25 ±125ps (maximum), CLK0

• Full 3.3V or 2.5V operating supply

• Lead-Free package available

• Industrial temperature information available upon request

ENERAL

ESCRIPTION

The ICS8705 is a highly versatile 1:8 Differen-

tial-to-LVCMOS/LVTTL Clock Generator and a

HiPerClockS™

member of the HiPerClockS™family of High Per-

formance Clock Solutions from ICS. The ICS8705

has two selectable clock inputs. The CLK1,

nCLK1 pair can accept most standard differential input lev-

els. The single ended CLK0 input accepts LVCMOS or LVTTL

input levels.The ICS8705 has a fully integrated PLL and can

be configured as zero delay buffer, multiplier or divider and

has an input and output frequency range of 15.625MHz to

250MHz. The reference divider, feedback divider and output

divider are each programmable, thereby allowing for the fol-

lowing output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2,

1:4, 1:8. The external feedback allows the device to achieve

“zero delay” between the input clock and the output clocks.

The PLL_SEL pin can be used to bypass the PLL for system

test and debug purposes. In bypass mode, the reference clock

is routed around the PLL and into the internal output dividers.

ICS

LOCK

IAGRAM

PLL_SEL

÷2, ÷4, ÷8, ÷16,

÷32

÷64, ÷128

SSIGNMENT

PLL_SEL

SEL3

DDO

GND

DDA

CLK0

CLK1

nCLK1

CLK_SEL

FB_IN

32 31 30 29 28 27 26 25

SEL0

9 10 11 12 13 14 15 16

DDO

GND

DDO

GND

PLL

SEL1

CLK0

CLK1

nCLK1

CLK_SEL

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

ICS8705

SEL0

FB_IN

SEL2

DDO

GND

DDO

SEL1

SEL2

SEL3

8705BY

32-Lead LQFP

7mm x 7mm x 1.4 mm

Y Package

Top View

www.icst.com/products/hiperclocks.html

REV. G JUNE 16, 2004

ICS8705BYLFT Related Products

	ICS8705BYLFT	ICS8705	ICS8705BY	ICS8705BYLF	ICS8705BYT
Description	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

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