EFR32BG21 Blue Gecko Wireless SoC
Family Data Sheet
The Blue Gecko family of SoCs is part of the Wireless Gecko port-
folio. Blue Gecko SoCs are ideal for enabling energy-friendly Blue-
tooth 5 networking for IoT devices.
The single-die solution combines an 80 MHz ARM Cortex-M33 with a high performance
2.4 GHz radio to provide an industry-leading, energy efficient wireless SoC for IoT con-
nected applications.
Blue Gecko applications include:
•
•
•
•
Lighting
Connected Home
Gateways and Digital Assistants
Building Automation and Security
KEY FEATURES
• 32-bit ARM® Cortex®-M33 core with 80
MHz maximum operating frequency
• Up to 1024 kB of flash and 96 kB of RAM
• 12-channel Peripheral Reflex System
enabling autonomous interaction of MCU
peripherals
• Integrated PA with up to 20 dBm (2.4
GHz) TX power
• Robust peripheral set and up to 20 GPIO
in a 4x4 QFN package
Core / Memory
ARM Cortex
TM
M33 processor
with DSP extensions,
FPU and TrustZone
HF Crystal
Oscillator
EM23 HF RC
Oscillator
LDMA
Controller
LF Crystal
Oscillator
Clock Management
HF
RC Oscillator
Fast Startup
RC Oscillator
Energy
Management
Voltage
Regulator
Security
Crypto Acceleration
Advanced Security
True Random
Number Generator
Security Core
Flash Program
Memory
Brown-Out
Detector
Ultra LF RC
Oscillator
LF
RC Oscillator
Power-On Reset
ETM
Debug Interface
RAM Memory
32-bit bus
Peripheral Reflex System
Radio Transceiver
RF Frontend
LNA
I
Q
PA
Serial
Interfaces
BUFC
DEMOD
FRC
USART
I/O Ports
External
Interrupts
General
Purpose I/O
Timers and Triggers
Timer/Counter
Protocol Timer
Analog I/F
ADC
PGA
IFADC
I
2
C
Low Energy Timer
Watchdog Timer
Analog
Comparator
AGC
CRC
PA
Frequency
Synth
MOD
RAC
Pin Reset
Real Time
Capture Counter
Back-Up Real
Time Counter
Pin Wakeup
Lowest power mode with peripheral operational:
EM0—Active
EM1—Sleep
EM2—Deep Sleep
EM3—Stop
EM4—Shutoff
silabs.com
| Building a more connected world.
Rev. 1.0
EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet
Feature List
1. Feature List
The EFR32BG21 highlighted features are listed below.
•
Low Power Wireless System-on-Chip
• High Performance 32-bit 80 MHz ARM Cortex
®
-M33 with
DSP instruction and floating-point unit for efficient signal
processing
• Up to 1024 kB flash program memory
• Up to 96 kB RAM data memory
• 2.4 GHz radio operation
• TX power up to 20 dBm
•
Low Energy Consumption
• 8.8 mA RX current at 2.4 GHz (1 Mbps GFSK)
• 9.3 mA TX current @ 0 dBm output power at 2.4 GHz
• 33.8 mA TX current @ 10 dBm output power at 2.4 GHz
• 50.9 μA/MHz in Active Mode (EM0)
• 5.0 μA EM2 DeepSleep current
(96 kB RAM retention and RTC running from LFXO)
• 4.5 μA EM2 DeepSleep current
(16 kB RAM retention and RTC running from LFRCO)
•
High Receiver Performance
• -97.5 dBm sensitivity @ 1 Mbit/s GFSK
• -94.4 dBm sensitivity @ 2 Mbit/s GFSK
• -104.9 dBm sensitivity @ 125 kbps GFSK
•
Supported Modulation Format
• GFSK
•
Protocol Support
• Bluetooth Low Energy (Bluetooth 5)
•
Wide selection of MCU peripherals
• 12-bit 1 Msps SAR Analog to Digital Converter (ADC)
• 2 × Analog Comparator (ACMP)
• Up to 20 General Purpose I/O pins with output state reten-
tion and asynchronous interrupts
• 8 Channel DMA Controller
• 12 Channel Peripheral Reflex System (PRS)
• 2 × 16-bit Timer/Counter
• 3 Compare/Capture/PWM channels
• 1 × 32-bit Timer/Counter
• 3 Compare/Capture/PWM channels
• 32-bit Real Time Counter
• 24-bit Low Energy Timer for waveform generation
• 2 × Watchdog Timer
• 3 × Universal Synchronous/Asynchronous Receiver/Trans-
mitter (UART/SPI/SmartCard(ISO 7816)/IrDA/I
2
S)
• 2 × I
2
C interface with SMBus support
•
Wide Operating Range
• 1.71 V to 3.8 V single power supply
• -40°C to 125°C ambient
•
Standard Security
• Hardware Cryptographic Acceleration for AES128/256,
SHA-1, SHA-2 (up to 256-bit), ECC (up to 256-bit), ECDSA
(up to 256-bit), ECDH, and J-Pake.
• True Random Number Generator (TRNG)
• ARM TrustZone
• Secure Boot
• Secure Debug Unlock
•
QFN32 4x4 mm Package
• 0.4 mm pitch
silabs.com
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Rev. 1.0 | 2
EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet
Ordering Information
2. Ordering Information
Table 2.1. Ordering Information
Max TX Power @ Fre-
Protocol Stack quency Band
Bluetooth 5
Bluetooth 5
Bluetooth 5
Bluetooth 5
Bluetooth 5
Bluetooth 5
10 dBm @ 2.4 GHz
10 dBm @ 2.4 GHz
10 dBm @ 2.4 GHz
20 dBm @ 2.4 GHz
20 dBm @ 2.4 GHz
20 dBm @ 2.4 GHz
Flash
(kB)
1024
512
768
1024
512
768
RAM
(kB)
96
64
64
96
64
64
Pack-
age
QFN32
QFN32
QFN32
QFN32
QFN32
QFN32
Ordering Code
EFR32BG21A010F1024IM32-B
EFR32BG21A010F512IM32-B
EFR32BG21A010F768IM32-B
EFR32BG21A020F1024IM32-B
EFR32BG21A020F512IM32-B
EFR32BG21A020F768IM32-B
Security
Standard
Standard
Standard
Standard
Standard
Standard
GPIO
20
20
20
20
20
20
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Rev. 1.0 | 3
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Introduction .
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. 6
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6
6
7
7
7
7
7
7
3.2 Radio . . . . . . . . . . . .
3.2.1 Antenna Interface . . . . . .
3.2.2 Fractional-N Frequency Synthesizer
3.2.3 Receiver Architecture . . . . .
3.2.4 Transmitter Architecture . . . .
3.2.5 Packet and State Trace . . . .
3.2.6 Data Buffering . . . . . . . .
3.2.7 Radio Controller (RAC). . . . .
3.3 General Purpose Input/Output (GPIO) .
3.4 Clocking . . . . . . . . . .
3.4.1 Clock Management Unit (CMU) .
3.4.2 Internal and External Oscillators.
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3.5 Counters/Timers and PWM . . . . . .
3.5.1 Timer/Counter (TIMER) . . . . .
3.5.2 Low Energy Timer (LETIMER) . . .
3.5.3 Real Time Clock with Capture (RTCC)
3.5.4 Back-Up Real Time Counter . . . .
3.5.5 Watchdog Timer (WDOG) . . . . .
3.6 Communications and Other Digital Peripherals . . . . . . . . . .
3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) .
3.6.2 Inter-Integrated Circuit Interface (I
2
C) . . . . . . . . . . . .
3.6.3 Peripheral Reflex System (PRS) . . . . . . . . . . . . .
3.7 Security Features . . . . . . . .
3.7.1 Standard Security . . . . . .
3.7.2 True Random Number Generator .
3.8 Analog. . . . . . . . . . . .
3.8.1 Analog Comparator (ACMP) . . .
3.8.2 Analog to Digital Converter (ADC) .
3.9 Reset Management Unit (RMU) .
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.10
.10
.10
.10
.10
.10
.10
.11
.11
.11
.11
.12
.13
3.10 Core and Memory . . . . . . . . . . . .
3.10.1 Processor Core . . . . . . . . . . . .
3.10.2 Memory System Controller (MSC) . . . . .
3.10.3 Linked Direct Memory Access Controller (LDMA)
3.11 Memory Map .
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3.12 Configuration Summary
4. Electrical Specifications
4.1 Electrical Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . 14
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.14
silabs.com
| Building a more connected world.
Rev. 1.0 | 4
4.1.1 Absolute Maximum Ratings . . . .
4.1.2 General Operating Conditions . . .
4.1.3 Thermal Characteristics . . . . .
4.1.4 Current Consumption . . . . . .
4.1.5 2.4 GHz RF Transceiver Characteristics
4.1.6 Flash Characteristics . . . . . .
4.1.7 Wake Up, Entry, and Exit times . . .
4.1.8 Oscillators . . . . . . . . . .
4.1.9 GPIO Pins (3V GPIO pins) . . . .
4.1.10 Analog to Digital Converter (ADC) .
4.1.11 Analog Comparator (ACMP) . . .
4.1.12 Temperature Sense . . . . . .
4.1.13 Brown Out Detectors . . . . . .
4.1.14 SPI Electrical Specifications . . .
4.1.15 I2C Electrical Specifications. . . .
4.2 Typical Performance Curves .
4.2.1 Supply Current . . . .
4.2.2 2.4 GHz Radio . . . .
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.14
.15
.16
.17
.22
.35
.36
.37
.42
.43
.45
.46
.47
.49
.50
.52
.53
.55
5. Typical Connection Diagrams
5.1 Power .
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. . . . . . . . . . . . . . . . . . . . . . . . 57
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.57
.57
.57
.58
.59
.59
5.2 RF Matching Networks . . . . . .
5.2.1 2.4 GHz 0 dBm Matching Network .
5.2.2 2.4 GHz 10 dBm Matching Network
5.2.3 2.4 GHz 20 dBm Matching Network
5.3 Other Connections.
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6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.1 QFN32 2.4GHz Device Pinout .
6.2 Alternate Function Table.
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.
6.3 Analog Peripheral Connectivity
6.4 Digital Peripheral Connectivity .
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.60
.61
.62
.63
7. QFN32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . .
7.1 QFN32 Package Dimensions .
7.2 QFN32 PCB Land Pattern .
7.3 QFN32 Package Marking
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66
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.70
8. Revision History
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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