82801CAM datasheet, PDF - EEWORLD Datasheet

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82801CAM: DescriptionMultifunction Peripheral, CMOS, PBGA421, 31 X 31 MM, BGA-421; CategoryThe embedded processor and controller Microcontrollers and processors; File Size3MB，546 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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82801CAM Overview

Multifunction Peripheral, CMOS, PBGA421, 31 X 31 MM, BGA-421

82801CAM Parametric

Parameter Name	Attribute value
Maker	Intel
Parts packaging code	BGA
package instruction	BGA,
Contacts	421
Reach Compliance Code	compliant
Address bus width	32
boundary scan	NO
Bus compatibility	USB; PCI; ISA
maximum clock frequency	66 MHz
External data bus width	32
JESD-30 code	S-PBGA-B421
length	31 mm
Number of I/O lines	32
Number of terminals	421
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
RAM (number of words)	256
Maximum seat height	2.59 mm
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	31 mm
Base Number Matches	1

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Intel

82801CAM I/O Controller

Hub 3 (ICH3-M)

Datasheet

July 2001

Document Number: 290716-001

Information in this document is provided in connection with Intel

products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel

I/O Controller Hub 3 (ICH3-M) component may contain design defects or errors known as errata which may cause the product to deviate

from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling

1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I

C bus/protocol and was developed by Intel.

Implementations of the I

C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips

Corporation.

Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.

Intel, Pentium, and Intel SpeedStep are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other

countries.

*Other names and brands may be claimed as the property of others.

Intel

82801CAM ICH3-M

Datasheet

Contents

Introduction

..........................................................................................................1-1

1.1

1.2

About This Datasheet ...................................................................................1-1

Overview .......................................................................................................1-3

Hub Interface to Host Controller ...................................................................2-3

Link to LAN Connect .....................................................................................2-3

EEPROM Interface .......................................................................................2-3

Firmware Hub Interface ................................................................................2-4

PCI Interface .................................................................................................2-4

IDE Interface .................................................................................................2-7

LPC I/F..........................................................................................................2-8

Interrupt Interface..........................................................................................2-8

USB Interface................................................................................................2-9

Power Management Interface.......................................................................2-9

Processor Interface.....................................................................................2-11

SMBus Interface .........................................................................................2-13

System Management Interface ...................................................................2-13

Real Time Clock Interface...........................................................................2-13

Other Clocks ...............................................................................................2-14

Miscellaneous Signals ................................................................................2-14

AC ’97 Link..................................................................................................2-14

General Purpose I/O ...................................................................................2-15

Power and Ground......................................................................................2-16

Pin Straps ...................................................................................................2-17

2.20.1 Functional Straps ...........................................................................2-17

2.20.2 External RTC Circuitry ...................................................................2-18

2.20.3 V5REF / Vcc3_3 Sequencing Requirements .................................2-18

2.20.4 Test Signals ...................................................................................2-19

2.20.4.1 Test Mode Selection.......................................................2-19

Power Planes................................................................................................3-1

Integrated Pull-Ups and Pull-Downs .............................................................3-2

IDE Integrated Series Termination Resistors................................................3-2

Output and I/O Signals Planes and States ...................................................3-3

Power Planes for Input Signals.....................................................................3-6

Signal Description

.............................................................................................2-1

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

2.14

2.15

2.16

2.17

2.18

2.19

2.20

Power Planes and Pin States

........................................................................3-1

3.1

3.2

3.3

3.4

3.5

Intel

ICH3 and System Clock Domains

...................................................4-1

Functional Description

....................................................................................5-1

5.1

Hub Interface to PCI Bridge (D30:F0)...........................................................5-1

5.1.1 PCI Bus Interface.............................................................................5-1

5.1.2 PCI-to-PCI Bridge Model .................................................................5-2

5.1.3 IDSEL to Device Number Mapping ..................................................5-2

5.1.4 SERR# Functionality........................................................................5-2

5.1.5 Parity Error Detection.......................................................................5-4

5.1.6 Standard PCI Bus Configuration Mechanism ..................................5-5

Intel

82801CAM ICH3-M

Datasheet

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