Error Detection And Correction Circuit, HST/T Series, 16-Bit, CMOS, CDFP28
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | Dynex |
| package instruction | DFP, FL28,.4 |
| Reach Compliance Code | unknown |
| series | HST/T |
| JESD-30 code | R-CDFP-F28 |
| JESD-609 code | e0 |
| Load capacitance (CL) | 50 pF |
| Logic integrated circuit type | ERROR DETECTION AND CORRECTION CIRCUIT |
| Number of digits | 16 |
| Number of functions | 1 |
| Number of terminals | 28 |
| Maximum operating temperature | 125 °C |
| Minimum operating temperature | -55 °C |
| Output characteristics | 3-STATE |
| Package body material | CERAMIC, METAL-SEALED COFIRED |
| encapsulated code | DFP |
| Encapsulate equivalent code | FL28,.4 |
| Package shape | RECTANGULAR |
| Package form | FLATPACK |
| Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
| power supply | 5 V |
| Certification status | Not Qualified |
| Filter level | 38535V;38534K;883S |
| Maximum supply voltage (Vsup) | 5.5 V |
| Minimum supply voltage (Vsup) | 4.5 V |
| Nominal supply voltage (Vsup) | 5 V |
| surface mount | YES |
| technology | CMOS |
| Temperature level | MILITARY |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | FLAT |
| Terminal pitch | 1.27 mm |
| Terminal location | DUAL |
| Maximum time at peak reflow temperature | NOT SPECIFIED |
| Base Number Matches | 1 |
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