DDR3 VLP UDIMM
VR7VUxx7258xBx
Features
JEDEC standard Power Supply
o
VDD = VDDQ = 1.5V ±0.075V
o
VDDSPD = +3.0V to +3.6V
240-pin Dual-In-Line Memory Module with parity bit for
address and control bus.
8 Internal Banks.
Programmable CAS Latency: 6, 7, 9, 10, 11, 12
Programmable CAS Write Latency (CWL).
Programmable Additive Latency (Posted CAS).
Fixed burst chop (BC) of 4 and burst length (BL) of 8 via
the mode register set (MRS)
Selectable BC4 or BL8 on-the-fly (OTF)
On-Die-Termination (ODT) and Dynamic ODT for improved
signal integrity.
Refresh. Self Refresh and Power Down Modes.
Serial Presence Detect with EEPROM.
On-DIMM Thermal Sensor.
VLP UDIMM dimensions: 133.35 mm x 18.75 mm.
RoHS Compliant* (see last page)
Nomenclature
Module Standard
PC3-6400
PC3 -8500
PC3-10600
PC3-12800
PC3-14900
SDRAM Standard
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
Clock
400MHz
533MHz
667MHz
800MHz
933MHz
Viking Technology¨2950 Red Hill Ave ¨ Costa Mesa, CA 92626
Office: 714.913.2200 Fax: 714.913.2202¨Website: http://www.vikingtechnology.com
This Data Sheet is subject to change without notice.
Doc. # PS7VUxx7258xBx
Revision B
Page 2 of 27
DDR3 VLP UDIMM
VR7VUxx7258xBx
PIN FUNCTION DESCRIPTION
SYMBOL
CK0, CK1
#CK0, #CK1
CKE[1:0]
TYPE
IN
IN
IN
POLARITY
Positive Edge
Negative Edge
Active High
DESCRIPTION
Positive line of the differential pair of system clock inputs.
Negative line of the differential pair of system clock inputs.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER
DOWN (row ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and disables decoder
when high. When decoder is disabled, new commands are ignored and previous
operations continue. These input signals also disable all outputs (except CKE and ODT)
of the register(s) on the DIMM when both inputs are high. When both S[1:0] are high, all
register outputs (except CKE, ODT and Chip select) remain in the previous state. For
modules supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of register
outputs.
On-Die Termination control signals
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the
operation to be executed by the SDRAM.
Reference voltage for DQ0-DQ63 and CB0-CB7.
Reference voltage for A0-A15, BA0-BA2, RAS#, CAS#, WE#, S0#, S1#, CKE0, CKE1,
Par_In, ODT0 and ODT1.
Selects which SDRAM bank of eight is activated. BA0 - BA2 define to which bank an
Active, Read, Write or Precharge command is being applied. Bank address also
determines mode register is to be accessed during an MRS cycle.
Provided the row address for Active commands and the column address
and Auto Precharge bit for Read/Write commands to select one location out of the
memory array in the respective bank. A10 is sampled during a Precharge command to
determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also
utilized for BL 4/8 identification for ‘’BL on the fly’’ during CAS# command. The address
inputs also provide the op-code during Mode Register Set commands.
Data and Check Bit Input/Output pins
Power and ground for the DDR SDRAM input buffers and core logic.
Masks write data when high, issued concurrently with input data.
Power and ground for the DDR SDRAM input buffers and core logic.
Termination Voltage for Address/Command/Control/Clock nets.
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
TDQS, TDQS# is applicable for X8 DRAMs only. When enabled via Mode Register
A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS,
TDQS# that is applied to DQS, DQS#. When disabled via mode register A11=0 in MR1,
DM, TDQS will provide the data mask function and TDQS# is not used. X4/X16 DRAMs
must disable the TDQS function via mode register A11=0 in MR1
These signals are tied at the system planar to either VSS or VDDSPD to configure the
serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DDSPD
on the system planar to act as a
pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to VDDSPD on the system planar to act as a pull-up.
This signal indicates that a thermal event has been detected in the thermal sensing
device.The system should guarantee the electrical level requirement is met for the
EVENT pin on TS/SPD part.
S[3:0]#
IN
Active Low
ODT[1:0]
RAS#, CAS#,
WE#
VREFDQ
VREFCA
BA[2:0]
IN
IN
Supply
Supply
IN
Active High
Active Low
-
A[15:13,
12/BC,11,
10/AP,9:0]
DQ [63:0],
CB [7:0]
VDD, VSS
DM [8:0]
VDD, VSS
VTT
DQS[17:0]
DQS [17:0]#
TDQS[17:9],
TDQS[17:9]#
SA [2:0]
SDA
SCL
EVENT#
IN
-
I/O
Supply
IN
Supply
Supply
I/O
I/O
OUT
-
-
Active High
Positive Edge
Negative Edge
IN
I/O
IN
OUT
(open drain)
-
-
-
Active Low
Viking Technology¨2950 Red Hill Ave ¨ Costa Mesa, CA 92626
Office: 714.913.2200 Fax: 714.913.2202¨Website: http://www.vikingtechnology.com
This Data Sheet is subject to change without notice.
Doc. # PS7VUxx7258xBx
Revision B
Page 4 of 27
DSP and ARM Processors
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