CT2-ML2LACW13C4 datasheet, PDF

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CT2-ML2LACW13C4: DescriptionFiber Optic Device,; CategoryWireless rf/communication Optical fiber; File Size119KB，7 Pages; ManufacturerLumentum Operations LLC

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CT2-ML2LACW13C4 Overview

Fiber Optic Device,

CT2-ML2LACW13C4 Parametric

Parameter Name	Attribute value
Objectid	4001059321
Reach Compliance Code	compliant

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Product Bulletin

2.5 Gb/s CWDM SFP

Transceiver (Multirate)

CT2 Series

The JDS Uniphase CT2 Series 2.5 Gb/s Coarse

Wavelength Division Multiplexing (CWDM)

transceiver integrates optics and electronics in a

Small Form Factor Pluggable (SFP) package. It is

Multisource Agreement (MSA) compatible and

designed for CWDM operation per ITU-T G.695

for unidirectional 8 channel black-link

transmission (S-C8S1-1DX and S-C8L1-1DX).

Although optimized for 2.5 Gb/s, the CT2

provides multi-rate capabilities and can be used

for various protocols ranging from OC-3 (155 Mb/s)

up to 2.7 Gb/s including 622 Mb/s, 1x/2x FC, GbE

and 2x GbE.

The CT2 Series CWDM SFP transceiver provides

a fully G.695 8 channel black-link compliant

interface between the optical Mux/Demux

photonic layer and the electrical layer. Its

microprocessor-based modular design

implements all features specified in the SFP MSA

compatible 2-wire Serial Digital Diagnostic

Monitoring Interface for Optical Transceivers.

The major components in this module include an

uncooled distributed feedback (DFB) based

optical transmitter, a PIN or APD based optical

receiver with integrated transimpedence

amplifier (TIA), an APD high voltage circuit (if

required), a microprocessor, a limiting post

amplifier, and a laser driver. This CWDM

transceiver design offers a "hot-pluggable"

interface and is available in short haul (40 km,

PIN) and long haul (80 km, APD) configurations.

Key Features

•

SFP MSA compatible

•

2.5 Gb/s compliant CWDM performance for

short haul and long haul

•

Microprocessor-based design fully implements

the Digital Diagnostic Monitoring Interface

•

Automatic output power and extinction ratio

control over temperature and lifetime to

compensate for laser efficiency degradation

•

Both PIN and APD versions meet -27 dB

receiver reflectance

•

Optical parameters tuned and optimized over

temperature in production test

Applications

•

Metro access

•

Metro core

•

Wide area networks

•

Optical crossconnects

Compliance

•

GR-253-CORE

•

ITU-T G.957

•

SFF-8472 Revision 9.3

•

ITU-T G.695

2.5 Gb/s CWDM SFP Transceiver | 2

Dimensions Diagram

(Specifications in mm unless otherwise noted; see dimensions table on next page.)

K REF

J MIN

F REF

Y MAX

H MAX

L MIN X 45°

Y MAX

G REF

Section A-A

R MAX

See Detail Y

X REF

AA REF

AE REF

AB MAX

Detail Y

Section Z-Z

2.5 Gb/s CWDM SFP Transceiver | 3

Dimension Table for the CT2

Designator

Dimension

13.7 mm

8.6 mm

8.5 mm

13.4 mm

1.0 mm

2.3 mm

4.2 mm

2.0 mm

28.5 mm

55.0 mm

1.1 mm x 45°

2.0 mm

2.25 mm

1.0 mm

9.2 mm

0.7 mm

45.0 mm

34.6 mm

41.8 mm

2.7 mm

7.3 mm

2.0 mm

0.45 mm

8.6 mm

2.6 mm

6.0 mm

Tolerance

±0.1 mm

Maximum

Reference

Maximum

Minimum

Reference

Minimum

±0.25 mm

±0.1 mm

Maximum

±0.2 mm

±0.3 mm

±0.15 mm

±0.05 mm

±0.1 mm

Reference

Maximum

±0.05 mm

Reference

Maximum

Reference

Comments

Transceiver width, nose piece or front that extends inside cage

Transceiver height, front, that extends inside cage

Transceiver height, rear

Transceiver width, rear

Extension of front sides outside of cage

Location of cage grounding springs from centerline, top

Location of side cage grounding springs from top

Width of cage grounding springs

Location of transition between nose piece and rear of transceiver

Transceiver overall length

Chamfer on bottom of housing

Height of rear shoulder from transceiver printed circuit board

Location of printed circuit board to bottom of transceiver

Thickness of printed circuit board

Width of printed circuit board

Width of skirt in rear of transceiver

Length from latch shoulder to rear of transceiver

Length from latch shoulder to bottom opening of transceiver

Length from latch shoulder to end of printed circuit board

Length from latch shoulder to shoulder of transceiver outside of cage

(location of positive stop)

Clearance for actuator tines

Transceiver length extending outside of cage

Maximum length of top and bottom transceiver extending outside of cage

Height of latch boss

Transceiver height, front, that extends inside the cage

Length of latch boss

Width of cavity that contains the actuator

Bail Latch Color Code Definition

Bail Latch Color

Gray

Violet

Blue

Green

Yellow

Orange

Red

Brown

Center Wavelength

1471 nm

1491 nm

1511 nm

1531 nm

1551 nm

1571 nm

1591 nm

1611 nm

Typical Reach

Short haul/Long haul

2.5 Gb/s CWDM SFP Transceiver | 4

CT2 Electrical Pad Layout

VeeT

TD-

TD+

VeeT

VccT

VccR

VeeR

RD+

RD-

VeeR

VeeT

Tx Fault

Tx Disable

MOD-DEF(2)

MOD-DEF(1)

MOD-DEF(0)

Rate Select

LOS

VeeR

Top of Board

Bottom of Board (As Viewed

through Top of Board)

Transceiver Pin Descriptions

TDb

RDb

Rate_select

TxDIS

LOS

Description

Un-clocked, multirate, differential serial bit stream (155 Mb/s to 2.7 Gb/s) used to drive the optical transmitter.

Internally AC coupled and terminated via internal 100

Ω

differential impedence.

Differential received electrical signal capable of detecting 155 Mb/s to 2.7 Gb/s bit patterns.

The differential pair is internally biased and AC coupled. This signal requires 100

Ω

external differential termination.

Internally monitored and available for future use. Can be customized for specific applications.

Transmitter Disable Input. A logic HIGH on this input pin disables the transmitter's laser so that there is no optical

output. If left open the transmitter will be disabled.

Loss of Signal (Open Collector). A logic HIGH on this output indicates an incoming signal level that is less than -25 dBm

but no greater than -31 dBm for the 40 km configuration and less than -34 dBm but no greater than -40 dBm for the 80 km

configuration. LOS shall deassert (logic LOW) when a 3 dB (maximum), 0.5 dB (minimum) hysteresis is obtained.

Transmitter fault (Open collector). A logic HIGH indicates that the transmitter is in a fault condition.

MOD_DEF(0) is internally grounded to indicate the presence of the module. Must be pulled-up on host board with

10 KΩ resistor.

MOD_DEF(1) is the clock of the 2 wire interface for module monitoring.

MOD_DEF(2) is the data line of the 2 wire interface for module monitoring.

Receiver, Transmitter power supply, respectively

Receiver, Transmitter ground, respectively. The chassis ground and circuit ground isolation is configurable.

Tx_fault

MOD_DEF(0)

MOD_DEF(1)

MOD_DEF(2)

VccR,VccT

VeeR, VeeT

2.5 Gb/s CWDM SFP Transceiver | 5

Absolute Maximum Ratings

Parameter

Standard operating case temperature range

Extended operating case temperature range

Storage case temperature range

Supply voltage

Voltage on any input/output pin

High-speed output source current

Lead soldering temperature/time

Operating relative humidity (non-condensing)

Receiver optical input power

APD

Minimum

0 °C

-5 °C

-40 °C

-0.5 V

Maximum

70 °C

85 °C

4.0 V

Vcc

50 mA

250 °C/10 seconds

85%

3 dBm

0 dBm

Transceiver Electrical Input/Output Characteristics (Vcc = 3.3 V±5%)

Parameter

Input data signal levels input voltage swing, DVIN (internally AC coupled)

Transmitter disable input (disabled/enabled)

Rate select input (high data rate/low data rate)

Transmitter fault output (asserted/deasserted)

Output data signal levels

output voltage swing, DVOUT (internally AC coupled)

Loss-of-signal output (output high, VOH/output low, VOL)

Minimum

200 mV

2.0 V/0 V

2.8 V/0 V

2.4 V/0 V

400 mV

2.4 V/0 V

Maximum

2000 mV

Vcc/0.8 V

Vcc/0.6 V

Vcc/0.5 V

2000 mV

Vcc/0.5 V

1. Terminated into 100

Ω

differential. These levels are guaranteed down to 2 dB lower than the typical receiver sensitivity for each data rate and reach.

Timing of Status and Control Input/Output

Parameter

TX_DISABLE assert time

TX_DISABLE deassert time

Time to initialize

TX_FAULT assert time

TX_DISABLE for reset

LOS assert time

LOS deassert time

2-wire serial clock rate

Symbol

t_off

t_on

t_init

t_fault

t_reset

t_loss_on

t_loss_off

f_serial_clock

Condition

Time from rising edge of TX_DISABLE to when the

output optical power falls below 10% of nominal

Time from falling edge of TX_DISABLE to when the

output optical power rises above 90% of nominal

Upon power up or negation of TX_FAULT due to TX_DISABLE

Time from a fault condition to TX_FAULT assertion

Time TX_DISABLE must be held HIGH to reset TX_FAULT

Time from loss of signal to assertion of LOS

Time from non-loss condition to LOS deassertion

Maximum

Minimum

Maximum

Specification

10 µs

1 ms

300 ms

100 µs

10 µs

100 µs

100 kHz

Power Supply Voltage

Parameter

Supply voltage

Minimum

Typical

Maximum

Typical

Maximum

1. Applies to hardware revision 2. Does not include output termination resistor current.

Short Haul (40 km, PIN)

3.1 V

3.3 V

3.5 V

275 mA

320 mA

Long Haul (80 km, APD)

3.1 V

3.3 V

3.5 V

285 mA

350 mA

Power supply current drain

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