K4B2G1646B-HPH9T datasheet, PDF

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K4B2G1646B-HPH9T: DescriptionCache DRAM Module, 128MX16, 0.255ns, CMOS, PBGA96, HALOGEN FREE AND ROHS COMPLIANT, FBGA-96; Categorystorage storage; File Size890KB，55 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/; Environmental Compliance

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K4B2G1646B-HPH9T Overview

Cache DRAM Module, 128MX16, 0.255ns, CMOS, PBGA96, HALOGEN FREE AND ROHS COMPLIANT, FBGA-96

K4B2G1646B-HPH9T Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Objectid	1126059861
package instruction	TFBGA, BGA96,9X16,32
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Maximum access time	0.255 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	667 MHz
I/O type	COMMON
interleaved burst length	8
JESD-30 code	R-PBGA-B96
JESD-609 code	e1
length	13.3 mm
memory density	2147483648 bit
Memory IC Type	CACHE DRAM MODULE
memory width	16
Humidity sensitivity level	1
Number of functions	1
Number of ports	1
Number of terminals	96
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	95 °C
Minimum operating temperature	-40 °C
organize	128MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA96,9X16,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	1.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	8
Maximum standby current	0.012 A
Maximum slew rate	0.3 mA
Maximum supply voltage (Vsup)	1.575 V
Minimum supply voltage (Vsup)	1.425 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	9 mm

K4B2G1646B-HPH9T Preview

K4B2G1646B

industrial

2Gb DDR3 SDRAM

2Gb B-die DDR3 SDRAM Specification

96 FBGA with Lead-Free & Halogen-Free

(RoHS Compliant)

Industrial Temp. -40 to 95°C

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE

CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-

WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-

OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT

GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

Page 1 of 55

Rev. 1.1 July 2009

K4B2G1646B

industrial

2Gb DDR3 SDRAM

Year

2009

- Initial release

- Added IDD6(PASR) data

History

Revision History

Revision

1.0

1.1

Month

March

July

Page 2 of 55

Rev. 1.1 July 2009

K4B2G1646B

industrial

2Gb DDR3 SDRAM

Table Contents

1.0 Ordering Information ....................................................................................................................5

2.0 Key Features ................................................................................................................................. 5

3.0 Package pinout/Mechanical Dimension & Addressing .............................................................6

3.1 x16 Package Pinout (Top view) : 96ball FBGA Package

....................................................................6

3.2 FBGA Package Dimension (x16)

.....................................................................................................7

4.0 Input/Output Functional Description ..........................................................................................8

5.0 DDR3 SDRAM Addressing ...........................................................................................................9

6.0 Absolute Maximum Ratings .......................................................................................................10

6.1 Absolute Maximum DC Ratings

....................................................................................................10

6.2 DRAM Component Operating Temperature Range

..........................................................................10

7.0 AC & DC Operating Conditions .................................................................................................10

7.1 Recommended DC operating Conditions (SSTL_1.5)

......................................................................10

8.0 AC & DC Input Measurement Levels .........................................................................................11

8.1 AC and DC Logic input levels for single-ended signals

...................................................................11

8.2 V

REF

Tolerances

.........................................................................................................................12

8.3 AC and DC Logic Input Levels for Ditterential Signals

.....................................................................13

8.3.1 Differential signal definition

................................................................................................13

8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)

...............................13

8.3.3 Single-ended requirements for differential signals

.................................................................14

8.4 Differential Input Cross Point Voltage

...........................................................................................15

8.5 Slew Rate Definition for Single Ended Input Signals

.......................................................................18

8.6 Slew rate definition for Differential Input Signals

............................................................................18

9.0 AC and DC Output Measurement Levels ..................................................................................16

9.1 Single Ended AC and DC Output Levels

........................................................................................16

9.2 Differential AC and DC Output Levels

...........................................................................................16

9.3.Single Ended Output Slew Rate

...................................................................................................16

9.4 Differential Output Slew Rate

.......................................................................................................17

9.5 Reference Load for AC Timing and Output Slew Rate

.....................................................................17

9.6 Overshoot/Undershoot Specification

............................................................................................18

9.6.1 Address and Control Overshoot and Undershoot specifications

..............................................18

9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot specifications

.................................18

9.7 34 ohm Output Driver DC Electrical Characteristics

........................................................................19

9.7.1 Output Drive Temperature and Voltage sensitivity

.................................................................20

9.8 On-Die Termination (ODT) Levels and I-V Characteristics

................................................................20

9.8.1 ODT DC electrical characteristics

.........................................................................................21

9.8.2 ODT Temperature and Voltage sensitivity

.............................................................................22

9.9 ODT Timing Definitions

...............................................................................................................23

9.9.1 Test Load for ODT Timings

.................................................................................................23

9.9.2 ODT Timing Definition

........................................................................................................23

10.0 Idd Specification Parameters and Test Conditions ...............................................................26

10.1 IDD Measurement Conditions

..................................................................................................26

10.2 IDD Specifications definition

...................................................................................................26

Page 3 of 55

Rev. 1.1 July 2009

K4B2G1646B

industrial

2Gb DDR3 SDRAM

11.0 2Gb DDR3 SDRAM B-die IDD Spec Table ...............................................................................35

12.0 Input/Output Capacitance ........................................................................................................36

13.0 Electrical Characteristics and AC timing for DDR3-1333 ......................................................37

13.1 Clock specification

.................................................................................................................37

13.1.1 Definition for tCK (avg)

.................................................................................................37

13.1.2 Definition for tCK (abs)

.................................................................................................37

13.1.3 Definition for tCH(avg) and tCL(avg)

...............................................................................37

13.1.4 Definition for note for tJIT(per), tJIT(per,lck)

...................................................................37

13.1.5 Definition for tJIT(cc), tJIT(cc,lck)

...................................................................................37

13.1.6 Definition for tERR(nper)

...............................................................................................37

13.2 Refresh Parameters by Device Density

.....................................................................................38

13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin

...........................................39

14.0 Timing Parameters by Speed Grade .......................................................................................40

14.1 Jitter Notes

............................................................................................................................43

14.2 Timing Parameter Notes

..........................................................................................................44

14.3 Address / Command Setup, Hold and Derating:

.........................................................................45

14.4 Data Setup, Hold and Slew Rate Derating:

.................................................................................51

Page 4 of 55

Rev. 1.1 July 2009

K4B2G1646B

1.0 Ordering Information

[ Table 1 ] Samsung 2Gb DDR3 B-die ordering information table

Organization

128Mx16

DDR3-1333 (9-9-9)

K4B2G1646B-HI(P)H9

industrial

2Gb DDR3 SDRAM

Package

96 FBGA

Note :

1. Speed bin is in order of CL-tRCD-tRP.

2. “I” of Part Number(13th digit) stand for Industrial Temp./Normal Power products.

3. “P” of Part Number(13th digit) stand for Industrial Temp./Low Power products.

2.0 Key Features

[ Table 2 ] 2Gb DDR3 B-die Speed bins

Speed

tCK(min)

CAS Latency

tRCD(min)

tRP(min)

tRAS(min)

tRC(min)

• JEDEC standard 1.5V ± 0.075V Power Supply

• V

DDQ

= 1.5V ± 0.075V

•

667MHz f

for 1333Mb/sec/pin

• 8 Banks

• Posted CAS

• Programmable CAS Latency(posted CAS): 9

• Programmable Additive Latency: 0, CL-2 or CL-1 clock

• Programmable CAS Write Latency (CWL) = 7

• 8-bit pre-fetch

• Burst Length: 8 (Interleave without any limit, sequential with starting

address “000” only), 4 with tCCD = 4 which does not allow seamless

read or write [either On the fly using A12 or MRS]

• Bi-directional Differential Data-Strobe

• Internal(self) calibration : Internal self calibration through ZQ pin

(RZQ : 240 ohm ± 1%)

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at -40°C < T

CASE

< 95

°C

• Asynchronous Reset

• Package : 96 balls FBGA - x16

• All of Lead-Free products are compliant for RoHS

• All of products are Halogen-Free

The 2Gb DDR3 SDRAM B-die is organized as a 8Mbit x 16 I/Os x 8 banks

device. This synchronous device achieves high speed double-data-rate

transfer rates of up to 1333Mb/sec/pin (DDR3-1333) for general applica-

tions.

Note : This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device

Operation & Timing Diagram”.

DDR3-1333

9-9-9

1.5

13.5

49.5

Unit

nCK

The chip is designed to comply with the following key DDR3 SDRAM fea-

tures such as posted CAS, Programmable CWL, Internal (Self) Calibra-

tion, On Die Termination using ODT pin and Asynchronous Reset .

All of the control and address inputs are synchronized with a pair of exter-

nally supplied differential clocks. Inputs are latched at the crosspoint of dif-

ferential clocks (CK rising and CK falling). All I/Os are synchronized with a

pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-

ion. The address bus is used to convey row, column, and bank address

information in a RAS/CAS multiplexing style. The DDR3 device operates

with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V V

DDQ

The 2Gb DDR3 B-die device is available in 96ball FBGA(x16)

Note : 1. The functionality described and the timing specifications included

in this data sheet are for the DLL Enabled mode of operation.

Page 5 of 55

Rev. 1.1 July 2009

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