6. Absolute Maximum Ratings .......................................................................................................................................... 11
6.1 Absolute Maximum DC Ratings............................................................................................................................... 11
6.2 DRAM Component Operating Temperature Range ................................................................................................ 11
7. AC & DC Operating Conditions..................................................................................................................................... 11
7.1 Recommended DC operating Conditions (SSTL_1.5)............................................................................................. 11
8. AC & DC Input Measurement Levels ............................................................................................................................ 12
8.1 AC and DC Logic input levels for single-ended signals ........................................................................................... 12
8.3 AC & DC Logic Input Levels for Differential Signals ................................................................................................ 14
8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .................................................. 14
8.3.3. Single-ended requirements for differential signals ........................................................................................... 15
8.4 Differential Input Cross Point Voltage...................................................................................................................... 16
8.5 Slew Rate Definition for Single Ended Input Signals............................................................................................... 16
8.6 Slew rate definition for Differential Input Signals ..................................................................................................... 16
9. AC and DC Output Measurement Levels...................................................................................................................... 17
9.1 Single Ended AC and DC Output Levels................................................................................................................. 17
9.2 Differential AC and DC Output Levels ..................................................................................................................... 17
9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 19
9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot specifications....................................................... 19
9.7 34 ohm Output Driver DC Electrical Characteristics................................................................................................ 20
9.7.1. Output Drive Temperature and Voltage sensitivity........................................................................................... 21
9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..................................................................................... 21
9.8.1. ODT DC electrical characteristics .................................................................................................................... 22
9.8.2. ODT Temperature and Voltage sensitivity ....................................................................................................... 23
9.9.1. Test Load for ODT Timings.............................................................................................................................. 24
10. IDD Specification Parameters and Test Conditions .................................................................................................... 27
14.1.1. Definition for tCK(avg).................................................................................................................................... 37
14.1.2. Definition for tCK(abs).................................................................................................................................... 37
14.1.3. Definition for tCH(avg) and tCL(avg) .............................................................................................................. 37
14.1.4. Definition for note for tJIT(per), tJIT(per, Ick) ................................................................................................. 37
14.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 37
14.1.6. Definition for tERR(nper)................................................................................................................................ 37
14.2 Refresh Parameters by Device Density................................................................................................................. 38
-3-
K4W2G1646B
datasheet
Rev. 1.22
gDDR3 SDRAM
14.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 38
14.3.1. Speed Bin Table Notes .................................................................................................................................. 39
15. Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ...................................................................... 40
15.3 Address / Command Setup, Hold and Derating: ................................................................................................... 45
15.4 Data Setup, Hold and Slew Rate Derating: ........................................................................................................... 51
16.3.2. Reset Initialization with Stable Power ............................................................................................................ 58
16.4.2.1. Burst Length, Type and Order ................................................................................................................. 60
16.4.2.2. CAS Latency............................................................................................................................................ 61
16.4.2.3. Test Mode................................................................................................................................................ 61
17. gDDR3 SDRAM Command Description and Operation .............................................................................................. 66
17.1 Command Truth Table........................................................................................................................................... 66
17.2 Clock Enable (CKE) Truth Table ........................................................................................................................... 67
17.3 No OPeration (NOP) Command ............................................................................................................................ 67
17.9 Extended Temperature Usage .............................................................................................................................. 75
17.9.1. Self-Refresh Temperature Range - SRT........................................................................................................ 75
17.10 Multi Purpose Register ........................................................................................................................................ 76
17.10.4. Protocol Example ......................................................................................................................................... 77
17.11 ACTIVE Command .............................................................................................................................................. 80
17.14.2.2. Data Setup and Hold Violations............................................................................................................. 91
17.14.2.3. Strobe to Strobe and Strobe to Clock Violations ................................................................................... 91
17.14.3. Write Data Mask........................................................................................................................................... 92
18.1 ODT Mode Register and ODT Truth Table............................................................................................................ 108
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