Rev. 1.0, Jan. 2010
K8P2716UZC
128Mb C-die Page NOR Flash
56Pin TSOP(20x14mm), 64ball FBGA (11x13, 1.0mm ball pitch)
Page Mode, (8M x16, 16Mb x8)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
ⓒ
2009 Samsung Electronics Co., Ltd. All rights reserved.
-1-
K8P2716UZC
datasheet
History
- Initial draft
- Ordering inforation revised
- ICC6 is changed from Typ. 6mA and Max. 10mA to Typ. 10mA and
Max. 15mA
- CFI (Common Flash Memory Interface Code) of address 2Dh
changed from 00FFh to 007Fh.
- Specification finalized
Rev. 1.0
NOR FLASH MEMORY
Revision History
Revision No.
0.0
0.1
Draft Date
Jul. 06, 2009
Oct. 05, 2009
Remark
Target
Target
Editor
-
-
1.0
Jan. 08, 2010
Final
-
-2-
K8P2716UZC
datasheet
Rev. 1.0
NOR FLASH MEMORY
Table Of Contents
128Mb C-die Page NOR Flash
1.0 FEATURES................................................................................................................................................................. 5
2.0 GENERAL DESCRIPTION ......................................................................................................................................... 5
3.0 PIN DESCRIPTION .................................................................................................................................................... 6
4.0 56TSOP PIN CONFIGURATION ................................................................................................................................ 7
5.0 64 Ball FBGA TOP VIEW (BALL DOWN) ................................................................................................................... 7
6.0 FUNCTIONAL BLOCK DIAGRAM .............................................................................................................................. 8
7.0 ORDERING INFORMATION ...................................................................................................................................... 9
8.0 PRODUCT INTRODUCTION...................................................................................................................................... 10
9.0 COMMAND DEFINITIONS ......................................................................................................................................... 11
10.0 DEVICE OPERATION .............................................................................................................................................. 16
10.1 Read Mode ............................................................................................................................................................ 16
10.2 Standby Mode ....................................................................................................................................................... 16
10.3 Output Disable....................................................................................................................................................... 16
10.4 Automatic Sleep Mode .......................................................................................................................................... 16
10.5 Autoselect Mode.................................................................................................................................................... 16
10.6 Write (Program/Erase) Mode................................................................................................................................. 17
10.6.1 Program .......................................................................................................................................................... 17
10.6.2 Writer Buffer Programming ............................................................................................................................. 18
10.6.3 Accelerated Program Operation...................................................................................................................... 19
10.6.4 Unlock Bypass ................................................................................................................................................ 20
10.6.5 Chip Erase ...................................................................................................................................................... 20
10.6.6 Block Erase ..................................................................................................................................................... 20
10.7 Erase Suspend / Resume...................................................................................................................................... 21
10.8 Program Suspend / Resume ................................................................................................................................. 21
10.9 Write Protect (WP)................................................................................................................................................. 22
10.10 Software Reset .................................................................................................................................................... 22
10.11 Hardware Reset................................................................................................................................................... 22
10.12 Power-up Protection ............................................................................................................................................ 23
10.13 Low Vcc Write Inhibit ........................................................................................................................................... 23
10.14 Write Pulse Glitch Protection............................................................................................................................... 23
10.15 Logical Inhibit....................................................................................................................................................... 23
11.0 COMMON FLASH MEMORY INTERFACE .............................................................................................................. 24
12.0 OTP BLOCK REGION .............................................................................................................................................. 24
12.1 OTP Block Protection ............................................................................................................................................ 24
13.0 ENHANCED BLOCK PROTECTION / UNPROTECTION ........................................................................................ 25
13.1 Block Protection..................................................................................................................................................... 26
13.2 Persistent Protection Bits ...................................................................................................................................... 26
13.3 Dynamic Protection Bits ........................................................................................................................................ 27
13.4 Persistent Protection Bit Lock Bit .......................................................................................................................... 27
13.5 Password Protection Method................................................................................................................................. 27
13.6 Master locking bit set............................................................................................................................................. 27
14.0 DEVICE STATUS FLAGS......................................................................................................................................... 36
15.0 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................... 39
16.0 RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND )......................................................... 39
17.0 DC CHARACTERISTICS.......................................................................................................................................... 40
18.0 CAPACITANCE(TA = 25
°
C, VCC = 3.0V, f = 1.0MHz) ............................................................................................ 40
19.0 AC TEST CONDITION.............................................................................................................................................. 41
20.0 AC CHARACTERISTICS .......................................................................................................................................... 41
20.1 Read Operations ................................................................................................................................................... 41
20.2 Write(Erase/Program)Operations .......................................................................................................................... 44
-3-
K8P2716UZC
datasheet
Rev. 1.0
NOR FLASH MEMORY
21.0 ERASE AND PROGRAM PERFORMANCE............................................................................................................. 45
22.0 PACKAGE DIMENSIONS......................................................................................................................................... 55
22.1 56-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE .................................................................... 55
22.2 64-Ball Fine Ball Grid Array Package (measured in millimeters)........................................................................... 56
-4-
K8P2716UZC
datasheet
Rev. 1.0
NOR FLASH MEMORY
128M Bit (8M x16, 16Mb x8) Page Mode / Page NOR Flash Memory
1.0 FEATURES
•
Single Voltage, 2.7V to 3.6V for Read and Write operations
•
Organization
8M x16 bit (Word mode)
16M x 8 bit (Byte mode)
•
Fast Read Access Time : 65ns
•
Page Mode Operation
8 Words Page access allows fast asychronous read
Page Read Access Time : 25ns
•
Uniform block architectures
64Kword x 128 (Uniform)
•
OTP Block : Extra 256 word
- 128word for factory and 128word for customer OTP
•
Power Consumption (typical value)
- Active Read Current : 30mA (@5MHz)
- Program/Erase Current : 25mA
- Standby Mode/Auto Sleep Mode : 20uA
•
Support Single & 32word Buffer Program
•
WP/ACC input pin
- Allows special protection of first or last block of flash array at V
IL
,
regardless of block protect status
- Removes special protection at V
IH,
the first or last block of flash array
return to normal block protect status
- Reduce program time at V
HH
: 6us/word at Write Buffer
•
Erase Suspend/Resume
•
Program Suspend/Resume
•
Unlock Bypass Mode
•
Hardware RESET Pin
•
Command Register Operation
•
Supports Common Flash Memory Interface
•
Industrial Temperature : -40°C to 85°C
•
Extended Temperature : -25°C to 85°C
•
Endurance : 100Kcycle
•
V
IO
options at 1.8V and 3V I/O
•
Package options
- 56 Pin TSOP (20x14mm)
- 64 Ball FBGA (11x13, 1.0mm Ball Pitch)
2.0 GENERAL DESCRIPTION
The K8P2716UZB featuring single 3.0V power supply, is an 128Mbit NOR-
type Flash Memory organized as 16M x 8 or 8M x16. The memory architec-
ture of the device is designed to divide its memory arrays into 128 blocks
with independent hardware protection. This block architecture provides
highly flexible erase and program capability. The K8P2716UZB NOR Flash
consists of uniform block.
The K8P2716UZB offers fast page access time of 25ns with random access
time of 65ns. The device′s fast access times allow high speed microproces-
sors to operate without wait states. The device performs a program opera-
tion in unit of 16 bits (Word) and erases in units of a block. Single or multiple
blocks can be erased. The block erase operation is completed within typi-
cally 0.7 sec. The device requires 25mA as program/erase current in the
commercial and extended temperature ranges.
The K8P2716UZB NOR Flash Memory is created by using Samsung's
advanced CMOS process technology. This device is available in 64FBGA
and 56 Pin TSOP. The device is compatible with EPROM applications to
require high-density and cost-effective nonvolatile read/write storage solu-
tions.
-5-
京公网安备 11010802033920号
EEWORLD
