3DD13005 datasheet, PDF - EEWORLD Datasheet

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3DD13005: DescriptionTransistor; CategoryDiscrete semiconductor The transistor; File Size280KB，3 Pages; ManufacturerJCET; Websitehttp://www.cj-elec.com/; Jiangsu Changdian Technology Co., Ltd. focuses on semiconductor packaging and testing business, providing customers at home and abroad with a full range of solutions such as chip testing, packaging design, packaging testing, etc. The company was successfully listed on the Shanghai Main Board in 2003, becoming the first semiconductor packaging and testing listed company in China. It now has a national enterprise technology center and a postdoctoral research workstation. It is a national key high-tech enterprise, a supporting unit of the National Engineering Laboratory for High-density Integrated Circuits, and the chairman unit of the Integrated Circuit Packaging Technology Innovation Strategic Alliance.

Discrete devices: diodes (switching diodes, Schottky diodes (Schottky rectifiers), voltage regulator diodes, Pin diodes, TVS diodes, rectifier diodes, fast recovery diodes); transistors (Darlington tubes, digital transistors, MOSFETs); thyristors: silicon-controlled rectifiers, triacs; composite tubes: transistors + field-effect tubes, dual transistors, dual digital transistors, digital transistors + transistors, transistors + diodes, field-effect tubes + diodes, dual field-effect tubes. Voltage regulator circuit; energy-saving lamp charger switch tube

Lead frame: TO series (TO); SOD series (SOD); SOT series (TSOT, SOT); FBP series (WBFBP); QFN series (QFNWB, DFNWB, DFNFC, QFNFC); QFP series (LQFP: PQFP: PLCC: TQFP); SIP series (SIP, HSIP, FSIP); SOP series (SOP, HSOP, SSOP, MSOP, HTSOP, TSSOP); DIP series (DIP, FDIP, SDIP); PDFN series; PQFN series; MIS series (MISFC, MISWB)

Nine core technologies: Through Silicon Via (TSV) packaging technology; SiP RF packaging technology; wafer-level 3D rewiring packaging process technology; copper bump interconnection technology; high-density FC-BGA packaging and testing technology (Flip Chip BGA); multi-turn array four-sided pinless packaging and testing technology; package body 3D stacking technology; 50μm or less ultra-thin chip 3D stacking packaging technology; MEMS multi-chip packaging technology; MIS packaging technology (pre-encapsulated interconnection system); BGA packaging technology, etc.

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3DD13005 Overview

Transistor

3DD13005 Parametric

Parameter Name	Attribute value
Maker	JCET
package instruction	,
Reach Compliance Code	unknown
Maximum collector current (IC)	4 A
Configuration	Single
Minimum DC current gain (hFE)	10
Maximum operating temperature	150 °C
Polarity/channel type	NPN
Maximum power dissipation(Abs)	1.5 W
surface mount	NO
Nominal transition frequency (fT)	5 MHz
Base Number Matches	1

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JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD

TO-220 Plastic-Encapsulate Transistors

3DD13005

TRANSISTOR（ NPN

）

TO—220

FEATURES

Power dissipation

1.5 W（Tamb=25℃）

Collector current

CM:

Collector-base voltage

(BR)CBO

: 700 V

Operating and storage junction temperature range

，T

stg

: -55℃ to +150℃

ELECTRICAL CHARACTERISTICS（Tamb=25℃

Parameter

Collector-base breakdown voltage

Collector-emitter breakdown voltage

Emitter-base breakdown voltage

Collector cut-off current

Emitter cut-off current

DC current gain

Collector-emitter saturation voltage

Base-emitter saturation voltage

Transition Frequency

Fall time

Storage time

Symbol

V(BR)

CBO

V(BR)

CEO

V(BR)

EBO

CBO

CEO

EBO

(sat)

1.BASE

2.COLLECTOR

3.EMITTER

123

unless

Test

otherwise

specified）

TYP

MAX

UNIT

1000

100

1000

µA

conditions

MIN

700

400

Ic= 1000 µA，I

Ic= 10

mA，I

= 1000 µA，I

= 700 V I

，

= 400 V I

，

V I

，

= 5 V, I

= 1000mA

=2000m A,I

=500 mA

=2000m A, I

= 500mA

=10 V, IC=500mA

0.6

1.6

MHz

0.9

µs

f = 1MHz

=-I

=0.4A, I

=2A

=120V

CLASSIFICATION OF h

Rank

Range

10-15

15-20

20-25

25-30

30-35

35-40

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