AT49F001ANT-55VU datasheet, PDF

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AT49F001ANT-55VU: DescriptionFlash, 128KX8, 55ns, PDSO32, 8 X 14 MM, GREEN, PLASTIC, MO-142BA, VSOP-32; Categorystorage storage; File Size414KB，18 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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AT49F001ANT-55VU Overview

Flash, 128KX8, 55ns, PDSO32, 8 X 14 MM, GREEN, PLASTIC, MO-142BA, VSOP-32

AT49F001ANT-55VU Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	TSOP1
package instruction	TSOP1,
Contacts	32
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	55 ns
JESD-30 code	R-PDSO-G32
JESD-609 code	e3
length	12.4 mm
memory density	1048576 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Programming voltage	5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
type	NOR TYPE
width	8 mm
Base Number Matches	1

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Features

•

Single-voltage Operation

– 5V Read

– 5V Reprogramming

Fast Read Access Time – 45 ns

Internal Program Control and Timer

Sector Architecture

– One 16K Bytes Boot Block with Programming Lockout

– Two 8K Bytes Parameter Blocks

– Two Main Memory Blocks (32K Bytes, 64K Bytes)

Fast Erase Cycle Time – 3 Seconds

Byte-by-Byte Programming – 30 µs/Byte Typical

Hardware Data Protection

DATA Polling for End of Program Detection

Low Power Dissipation

– 30 mA Active Current

– 50 µA CMOS Standby Current

Typical 10,000 Write Cycles

Green (Pb/Halide-free) Packaging Option

•

1-megabit

(128K x 8)

5-volt Only

Flash Memory

AT49F001A

AT49F001AN

AT49F001AT

AT49F001ANT

Not Recommended

for New Design

Contact

Atmel to discuss

the latest design in trends

and options

•

1. Description

The AT49F001A(N)(T) is a 5-volt only in-system reprogrammable Flash memory. Its

1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with

Atmel’s advanced nonvolatile CMOS technology, the device offers access times to

45 ns with power dissipation of just 165 mW over the industrial temperature range.

When the device is deselected, the CMOS standby current is less than 50 µA. For the

AT49F001AN(T), pin 1 for the PLCC package and pin 9 for the TSOP package are no

connect pins.

To allow for simple in-system reprogrammability, the AT49F001A(N)(T) does not

require high input voltages for programming. Five-volt-only commands determine the

read and programming operation of the device. Reading data out of the device is sim-

ilar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus

contention. Reprogramming the AT49F001A(N)(T) is performed by erasing a block of

data and then programming on a byte by byte basis. The byte programming time is a

fast 30 µs. The end of a program cycle can be optionally detected by the DATA polling

feature. Once the end of a byte program cycle has been detected, a new access for a

read or program can begin. The typical number of program and erase cycles is in

excess of 10,000 cycles.

The device is erased by executing the erase command sequence; the device inter-

nally controls the erase operations. There are two 8K byte parameter block sections,

two main memory blocks, and one boot block.

The device has the capability to protect the data in the boot block; this feature is

enabled by a command sequence. The 16K-byte boot block section includes a repro-

gramming lock out feature to provide data integrity. The boot sector is designed to

contain user secure code, and when the feature is enabled, the boot sector is

protected from being reprogrammed.

3365E–FLASH–4/05

4.4

Erasure

Before a byte can be reprogrammed, the main memory block or parameter block which contains

the byte must be erased. The erased state of the memory bits is a logical “1”. The entire device

can be erased at one time by using a 6-byte software code. The software chip erase code con-

sists of 6-byte load commands to specific address locations with a specific data pattern (please

refer to the Chip Erase Cycle Waveforms).

After the software chip erase has been initiated, the device will internally time the erase opera-

tion so that no external clocks are required. The maximum time needed to erase the whole chip

is t

. If the boot block lockout feature has been enabled, the data in the boot sector will not be

erased.

4.4.1

Chip Erase

If the boot block lockout has been enabled, the Chip Erase function will erase Parameter Block

1, Parameter Block 2, Main Memory Block 1- 2 but not the boot block. If the Boot Block Lockout

has not been enabled, the Chip Erase function will erase the entire chip. After the full chip erase

the device will return back to read mode. Any command during chip erase will be ignored.

4.4.2

Sector Erase

As an alternative to a full chip erase, the device is organized into sectors that can be individually

erased. There are two 8K-byte parameter block sections and two main memory blocks. The 8K-

byte parameter block sections and the two main memory blocks can be independently erased

and reprogrammed. The Sector Erase command is a six bus cycle operation. The sector

address is latched on the rising WE edge of the sixth cycle and the 30H data input command is

also latched at the rising edge of WE. The sector erase starts after the rising edge of WE of the

sixth cycle. The erase operation is internally controlled; it will automatically time to completion.

4.5

Byte Programming

Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte

basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations

can convert “0”s to “1”s. Programming is accomplished via the internal device command register

and is a 4 bus cycle operation (please refer to the

“Command Definition Table” on page 6).

The

device will automatically generate the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs

last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming

is completed after the specified t

cycle time. The DATA polling feature may also be used to

indicate the end of a program cycle.

4.6

Boot Block Programming Lockout

The device has one designated block that has a programming lockout feature. This feature pre-

vents programming of data in the designated block once the feature has been enabled. The size

of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that

is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the

device while data in the rest of the device is updated. This feature does not have to be activated;

the boot block’s usage as a write protected region is optional to the user. The address range of

the boot block is 00000 to 03FFF for the AT49F001A(N) while the address range of the boot

block is 1C000 to 1FFFF for the AT49F001A(N)T.

Once the feature is enabled, the data in the boot block can no longer be erased or programmed

with input voltage levels of 5.5V or less. Data in the main memory block can still be changed

AT49F001A(N)(T)

3365E–FLASH–4/05

AT49F001A(N)(T)

through the regular programming method. To activate the lockout feature, a series of six pro-

gram commands to specific addresses with specific data must be performed. Please refer to the

“Command Definition Table” on page 6.

4.6.1

Boot Block Lockout Detection

A software method is available to determine if programming of the boot block section is locked

out. When the device is in the software product identification mode (see Software Product Iden-

tification Entry and Exit sections) a read from address location 00002H will show if programming

the boot block is locked out for the AT49F001A(N), and a read from address location 1C002H

will show if programming the boot block is locked out for the AT49F001A(N)T. If the data on I/O0

is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout fea-

ture has been activated and the block cannot be programmed. The software product

identification exit code should be used to return to standard operation.

Boot Block Programming Lockout Override

The user can override the boot block programming lockout by taking the RESET pin to 12 volts.

By doing this, protected boot block data can be altered through a chip erase, sector erase or

word programming. When the RESET pin is brought back to TTL levels the boot block program-

ming lockout feature is again active. This feature is not available on the AT49F001AN(T).

4.6.2

4.7

Product Identification

The product identification mode identifies the device and manufacturer as Atmel. It may be

accessed by hardware or software operation. The hardware operation mode can be used by an

external programmer to identify the correct programming algorithm for the Atmel product.

For details, see

“Operating Modes” on page 7

(for hardware operation) or Software Product

Identification. The manufacturer and device code is the same for both modes.

4.8

DATA Polling

The AT49F001A(N)(T) features DATA polling to indicate the end of a program cycle. During a

program cycle an attempted read of the last byte loaded will result in the complement of the

loaded data on I/O7. Once the program cycle has been completed, true data is valid on all out-

puts and the next cycle may begin. DATA polling may begin at any time during the program

cycle.

4.9

Toggle Bit

In addition to DATA polling the AT49F001A(N)(T) provides another method for determining the

end of a program or erase cycle. During a program or erase operation, successive attempts to

read data from the device will result in I/O6 toggling between one and zero. Once the program

cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit

may begin at any time during a program cycle.

4.10

Hardware Data Protection

Hardware features protect against inadvertent programs to the AT49F001A(N)(T) in the follow-

ing ways: (a) V

sense: if V

is below 3.8V (typical), the program function is inhibited. (b)

Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c)

Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program

cycle.

3365E–FLASH–4/05

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