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9248G-150-T

Description
Clock Generator, PDSO48
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size147KB,11 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

9248G-150-T Overview

Clock Generator, PDSO48

9248G-150-T Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Objectid109007512
package instructionTSSOP, TSSOP48,.3,20
Reach Compliance Codenot_compliant
ECCN codeEAR99
JESD-30 codeR-PDSO-G48
JESD-609 codee0
Humidity sensitivity level1
Number of terminals48
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP48,.3,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)240
power supply3.3 V
Certification statusNot Qualified
Maximum slew rate250 mA
Nominal supply voltage3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature20
Integrated
Circuit
Systems, Inc.
ICS9248-150
Frequency Generator for Multi-Processor Servers
Recommended Application:
ServerWorks Grand Champion Systems
Output Features:
8 - Differential CPU Clock Pairs @ 3.3V
1 - 3V 33MHz PCI clocks
1 - 48MHz clock
1 - Inverted 48MHz clock
1 - 14.318MHz reference output
Features:
Up to 200MHz frequency support
Support power management: Power Down Mode
Supports Spread Spectrum modulation: 0 to -0.5%
down spread.
Uses external 14.318MHz crystal
Select logic for Differential Swing Control, Test mode,
Tristate, Power down, Spread Spectrum.
External resistor for current reference
FS pins for frequency select
Key Specifications:
PCI Output jitter <500ps
CPU Output jitter <150ps
48MHz Output jitter <350ps
REF Output jitter < 1000ps
PCICLK
VDD48
FS0/48MHz
FS1/48MHz#
GND48
VDDCPU
CPUCLKT0
CPUCLKC0
GNDCPU
CPUCLKT1
CPUCLKC1
VDDCPU
CPUCLKT2
CPUCLKC2
GNDCPU
CPUCLKT3
CPUCLKC3
VDDCPU
REF
SPREAD#
GNDREF
X1
X2
VDDREF
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL100/133
GNDPCI
VDDA
GNDA
PD#
VDDCPU
CPUCLKT4
CPUCLKC4
GNDCPU
CPUCLKT5
CPUCLKC5
VDDCPU
CPUCLKT6
CPUCLKC6
GNDCPU
CPUCLKT7
CPUCLKC7
VDDCPU
MULTSEL0
MULTSEL1
GND
GNDI REF
I REF
VDDI REF
48-Pin SSOP and TSSOP
Functionality
SEL133/100
0
0
0
0
1
1
1
1
FS0
0
0
1
1
0
0
1
1
FS1
0
1
0
1
0
1
0
1
Function
Active 100MHz
100MHz Test Mode
100MHz Test Mode
Tristate all outputs
Active 133MHz
133MHz Test Mode
Active 200MHz
Reser ved
Block Diagram
PLL2
ICS9248-150
48MHz
48MHz#
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
REF
CPU
DIVDER
8
8
CPUCLKT (7:0)
CPUCLKC (7:0)
PCICLK
Analog Power Groups
VDD48, GND48 = 48MHz, PLL2
VDDA=VDD (core supply voltage 3.3V)
GNDA=Ground for core supply
PCI
DIVDER
Digital Power Group
VDDREF, GNDREF = REF, Xtal
PD#
SPREAD#
MULTSEL(1:0)
SEL100/133
FS(1:0)
Control
Logic
Config.
Reg.
I REF
0352F—03/29/06
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