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5962G9651203QXC

Description
NAND Gate,
Categorylogic    logic   
File Size135KB,12 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

5962G9651203QXC Overview

NAND Gate,

5962G9651203QXC Parametric

Parameter NameAttribute value
Objectid8005430461
package instruction,
Reach Compliance Codeunknown
Country Of OriginUSA
YTEOL5.1
seriesAC
JESD-30 codeR-CDFP-F14
length8.636 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.008 A
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Encapsulate equivalent codeFL14,.25
Package shapeRECTANGULAR
Package formFLATPACK
Maximum supply current (ICC)10 mA
Prop。Delay @ Nom-Sup9 ns
propagation delay (tpd)9 ns
Certification statusQualified
Schmitt triggerNO
Filter levelMIL-PRF-38535 Class Q
Maximum seat height2.5654 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.6 V
surface mountYES
technologyCMOS
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
total dose500k Rad(Si) V
width6.477 mm
UT54ACS00E/UT54ACTS00E
Quadruple 2-Input NAND Gates
December 2014
www.aeroflex.com/Logic
Datasheet
FEATURES
0.6μm
CRH CMOS process
- Latchup immune
• High speed
• Low power consumption
• Wide power supply operating range from 3.0V to 5.5V
• Available QML Q or V processes
• 14-lead flatpack
• UT54ACS00E-SMD- 5962-96512
• UT54ACTS00E-SMD- 5962-96513
DESCRIPTION
The UT54ACS00E and the UT54ACTS00E are quadruple,
two-input NAND gates. The circuits perform the Boolean func-
tions Y = A⋅B or Y = A + B in positive logic.
The device is characterized over full military temperature range
of -55°C to +125°C.
LOGIC SYMBOL
(1)
(2)
(4)
(5)
(9)
(10)
(12)
(13)
(11)
(6)
(8)
Y2
Y3
Y4
A1
B1
A2
B2
A3
B3
A4
B4
&
(3)
Y1
FUNCTION TABLE
INPUTS
A
H
L
X
B
H
X
L
OUTPUT
Y
L
H
H
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
LOGIC DIAGRAM
PINOUT
14-Lead Flatpack
TopView
A1
B1
Y1
A2
B2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B4
A4
Y4
B3
A3
Y3
A1
B1
A2
B2
A3
B3
A4
B4
Y1
Y2
Y3
Y4
36-00-04-005
Ver. 1.0.0
1
Aeroflex Microelectronics Solutions - HiRel

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