Multilayer ceramic capacitors
ESD robust, X7R, case sizes 0603 and 0805
Series/Type:
Chip
Ordering code: B379**E
Date:
Version:
25.02.2009
3, preliminary data sheet
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Identification/Classification 2: (header 2)
Ordering code:
Series/Type:
Preliminary data (optional): (if necessary)
Department:
Date:
Prepared by:
Release signed PE:
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Multilayer ceramic capacitors
ESD robust, X7R, case sizes 0603 and 0805
B379**E
Chip
Preliminary
KB VS PE
2009-02-25
Mr. Schrotter
Dr. Engel
Mr. Schlauer
New edition
X
X
©
EPCOS AG 2009. Reproduction, publication and dissemination of this data sheet, enclosures hereto and the
information contained therein without EPCOS' prior express consent is prohibited.
Multilayer ceramic capacitors
ESD robust, X7R, case sizes 0603 and 0805
Preliminary
B379**E
Chip
Ordering code
B37941
Type and size:
E
1
103
K
0
60
931
≙
X7R / 0603
941
≙X7R
/ 0805
E
≙
ESD robust
Termination:
nickel barrier
Rated voltage:
5
≙
50 VDC
1
≙
100 VDC
Rated capacitance (example):
103
≙
10 · 10
3
pF (10 nF)
Capacitance tolerance:
K
≙
±10 %
Internal coding:
0
Packaging code:
60
≙
cardboard tape, 180-mm reel
70
≙
cardboard tape, 330-mm reel
62
≙
blister tape, 180-mm reel
72
≙
blister tape, 330-mm reel
KB VS PE
Please read Cautions
and warnings
and
Important notes
at the end of this document.
Page 2 of 13
2009-02-25
Multilayer ceramic capacitors
ESD robust, X7R, case sizes 0603 and 0805
Preliminary
Features
High ESD and pulse strength
Reduced DC bias dependence
High volumetric efficiency
Non-linear capacitance change
High insulation resistance
B379**E
Chip
Applications
Interference suppression for input circuits
Blocking and coupling
Decoupling
Termination
For soldering: Nickel barrier terminations (Ni)
Delivery mode
Cardboard and blister tape (blister tape for chip thickness
≥1.2
±0.1 mm),
180-mm and 330-mm reel available
Electrical data
Temperature characteristic:
Climatic category (IEC 60068-1):
Standard:
Dielectric:
Rated voltage:
Capacitance test conditions
Test frequency:
Test voltage:
Max. relative capacitance change:
Dissipation factor tanδ (limit value):
Insulation resistance
1)
at +25°C:
Time constant
1)
τ
at +25 °C:
Operating temperature range:
Capacitance values:
Ageing
2)
:
X7R
55/125/56
EIA
Class 2
50; 100 VDC
(1.0 ± 0.2) kHz
(1.0 ± 0.2) V
RMS
±15%
< 25 · 10
-3
>10
5
MΩ
>1000 s
–55 °C ... +125 °C
1 nF … 10 nF
yes
1)
2)
For C
R
>10 nF the time constant
τ
= C · R
ins
is given.
Subject to aging, please refer to “General Technical Information” at
www.epcos.com/ceramic_capacitors
or data book
2009-02-25
Page 3 of 13
“Multilayer Ceramic Capacitors”.
KB VS PE
Please read Cautions
and warnings
and
Important notes
at the end of this document.
Multilayer ceramic capacitors
ESD robust, X7R, case sizes 0603 and 0805
Preliminary
Typical ESD Levels
AEC-Q200
1 x + and 1 x -
150 pF / 2 kΩ
18 kV
9 kV
25 kV
MIL-STD-883G
3 x + and 3 x -
150 pF / 330
Ω
18 kV
9 kV
25 kV
B379**E
Chip
B37931E5103K0**
B37941E1102K0**
B37941E1103K0**
ISO 10605
10 x + and 10 x -
10 x + and 10 x -
150 pF / 330
Ω
300 pF / 2 kΩ
15 kV
6 kV
5 kV
4 kV
22 kV
14 kV
Table 1: typical ESD levels for ESD robust MLCC’s
With respect to the ESD test conditions as described in this specification, the typical ESD levels in
table 1
are
applicable.
After each ESD pulse the MLCC is discharged through a 1 MΩ resistor. The interval between two subsequent
ESD pulses is set to 5 seconds. The number of the subsequent ESD pulses is defined in
table 3.
For more
details see chapter
ESD strength
on page 10.
DC – Bias
The special design of ESD robust MLCC series ensures reduced DC bias dependence with respect to standard
X7R MLCC’s.
The thus available larger residual capacitance under DC-Bias enables ESD robustness, furthermore higher
stability of filter characteristics.
KB VS PE
Please read Cautions
and warnings
and
Important notes
at the end of this document.
Page 4 of 13
2009-02-25
Multilayer ceramic capacitors
ESD robust, X7R, case sizes 0603 and 0805
Preliminary
Attenuation
A common application of MLCC is for EMC filtering.
The attenuation of the ESD robust MLCC is shown in
figure 1.
B379**E
Chip
0
-10
Insertion Loss shunt S12 [dB]
-20
-30
-40
-50
-60
0603_10nF
0805_10nF
0805_1nF
1
10
100
1000
10000
-70
Frequency [MHz]
Figure 1: Attenuation of ESD robust MLCC’s
KB VS PE
Please read Cautions
and warnings
and
Important notes
at the end of this document.
Page 5 of 13
2009-02-25
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