74LVT573
3.3 V octal D-type transparent latch; (3-state)
Rev. 04 — 15 September 2008
Product data sheet
1. General description
The 74LVT573 is a high-performance BiCMOS product designed for V
CC
operation at
3.3 V. This device is an octal transparent latch coupled to eight 3-state output buffers. The
two sections of the device are controlled independently by Latch Enable (LE) and Output
Enable (OE) control gates. The 74LVT573 has a broadside pinout configuration to
facilitate PC board layout and allow easy interface with microprocessors.
The data on the D inputs are transferred to the latch outputs when the Latch Enable (LE)
input is High. The latch remains transparent to the data inputs while LE is High, and stores
the data that is present one setup time before the High-to-Low enable transition.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all
eight 3-state buffers independent of the latch operation.
When OE is Low, the latched or transparent data appears at the outputs. When OE is
High, the outputs are in the High-impedance “OFF” state, which means they will neither
drive nor load the bus.
2. Features
I
I
I
I
I
I
I
I
I
I
I
Inputs and outputs arranged for easy interfacing to microprocessors
3-state outputs for bus interfacing
Common output enable control
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
No bus current loading when output is tied to 5 V bus
Power-up reset
Power-up 3-state
Latch-up protection
N
JESD78 class II exceeds 500 mA
I
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
I
Specified from
−40 °C
to +85
°C
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVT573D
74LVT573DB
74LVT573PW
74LVT573BQ
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
SO20
SSOP20
TSSOP20
DHVQFN20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1
Type number
plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals;
body 2.5
×
4.5
×
0.85 mm
4. Functional diagram
11
1
1
2
3
4
5
6
7
8
9
OE
D0
D1
D2
D3
D4
D5
D6
D7
LE
11
mna807
C1
EN1
2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
4
5
6
7
8
9
3
1D
19
18
17
16
15
14
13
12
mna808
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVT573_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 15 September 2008
2 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LE LE
LATCH
2
LE LE
LATCH
3
LE LE
LATCH
4
LE LE
LATCH
5
LE LE
LATCH
6
LE LE
LATCH
7
LE LE
LATCH
8
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna810
Fig 3.
Logic diagram
5. Pinning information
5.1 Pinning
74LVT573
74LVTH573
terminal 1
index area
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
GND
(1)
GND 10
LE 11
13 Q6
12 Q7
OE
2
3
4
5
6
7
8
9
1
D0
D1
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
001aah713
74LVT573
74LVTH573
D2
D3
D4
D5
D6
D7
GND 10
001aah712
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 4.
Pin configuration for SO20, and (T)SSOP20
Fig 5.
Pin configuration for DHVQFN20
74LVT573_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 15 September 2008
3 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
5.2 Pin description
Table 2.
Symbol
OE
D0 to D7
GND
LE
Q0 to Q7
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
19, 18, 17, 16, 15, 14, 13, 12
20
Description
output enable input (active LOW)
data input
ground (0 V)
latch enable (active HIGH)
data output
supply voltage
6. Functional description
6.1 Function table
Table 3.
Function table
[1]
Control OE
L
L
L
H
Control LE
H
↓
L
X
Input Dn
L
H
l
h
Hold
Disable outputs
[1]
H = HIGH voltage level;
L = LOW voltage level;
↓
= HIGH-to-LOW latch enable transition;
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition;
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition;
Z = high-impedance OFF-state;
NC = no change;
X = don’t care.
Operating mode
Load and read register
enable
Latch and read register
Internal register Output Qn
L
H
L
H
NC
NC
L
H
L
H
NC
Z
X
X
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
output in HIGH-state
[1]
[1]
Conditions
Min
−0.5
−0.5
−0.5
-
-
-
-
Max
+4.6
+7.0
+7.0
−50
−50
128
−64
Unit
V
V
V
mA
mA
mA
mA
74LVT573_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 15 September 2008
4 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
Table 4.
Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
T
stg
T
j
P
tot
[1]
[2]
[3]
Parameter
storage temperature
junction temperature
total power dissipation
Conditions
[2]
Min
−65
-
-
Max
+150
150
500
Unit
°C
°C
mW
T
amb
=
−40 °C
to +85
°C
[3]
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
For SO20 packages: above 70
°C
derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60
°C
derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60
°C
derate linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
T
amb
∆t/∆V
Recommended operating conditions
Parameter
supply voltage
input voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
current duty cycle
≤
50 %; f
i
≥
1 kHz
ambient temperature
input transition rise and fall rate
in free air
outputs enabled
Conditions
Min
2.7
0
2.0
-
-
-
-
−40
-
Typ
-
-
-
-
-
-
-
-
-
Max
3.6
5.5
-
0.8
−32
32
64
+85
10
Unit
V
V
V
V
mA
mA
mA
°C
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IK
V
OH
input clamping voltage
HIGH-level output voltage
Conditions
V
CC
= 2.7 V; I
IK
=
−18
mA
V
CC
= 2.7 V to 3.6 V;
I
OH
=
−100 µA
V
CC
= 2.7 V; I
OH
=
−8
mA
V
CC
= 3.0 V; I
OH
=
−32
mA
V
OL
LOW-level output voltage
V
CC
= 2.7 V; I
OL
= 100
µA
V
CC
= 2.7 V; I
OL
= 24 mA
V
CC
= 3.0 V I
OL
= 16 mA
V
CC
= 3.0 V I
OL
= 32 mA
V
CC
= 3.0 V I
OL
= 64 mA
V
OL(pu)
power-up LOW-level
output voltage
V
CC
= 3.6 V; I
O
= 1 mA;
V
I
= GND or V
CC
[2]
T
amb
=
−40 °C
to +85
°C
Min
−1.2
Typ
[1]
−0.9
Max
-
-
-
-
0.2
0.5
0.4
0.5
0.55
0.55
Unit
V
V
V
V
V
V
V
V
V
V
V
CC
−
0.2 V
CC
−
0.1
2.4
2.0
-
-
-
-
-
-
2.5
2.2
0.1
0.3
0.25
0.3
0.4
0.13
74LVT573_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 15 September 2008
5 of 16
京公网安备 11010802033920号
EEWORLD
