EE PLD, 20ns, CMOS, CDIP24, 0.250 X 1.250 INCH, SKINNY, CERAMIC, DIP-24
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Parts packaging code | DIP |
| package instruction | DIP, |
| Contacts | 24 |
| Reach Compliance Code | unknow |
| ECCN code | 3A001.A.2.C |
| Other features | VARIABLE PRODUCT TERMS; 10 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET |
| maximum clock frequency | 33.3 MHz |
| JESD-30 code | R-GDIP-T24 |
| length | 31.9405 mm |
| Dedicated input times | 11 |
| Number of I/O lines | 10 |
| Number of terminals | 24 |
| Maximum operating temperature | 125 °C |
| Minimum operating temperature | -55 °C |
| organize | 11 DEDICATED INPUTS, 10 I/O |
| Output function | MACROCELL |
| Package body material | CERAMIC, GLASS-SEALED |
| encapsulated code | DIP |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
| Programmable logic type | EE PLD |
| propagation delay | 20 ns |
| Certification status | Not Qualified |
| Maximum seat height | 5.08 mm |
| Maximum supply voltage | 5.5 V |
| Minimum supply voltage | 4.5 V |
| Nominal supply voltage | 5 V |
| surface mount | NO |
| technology | CMOS |
| Temperature level | MILITARY |
| Terminal form | THROUGH-HOLE |
| Terminal pitch | 2.54 mm |
| Terminal location | DUAL |
| Maximum time at peak reflow temperature | NOT SPECIFIED |
| width | 7.62 mm |
| Base Number Matches | 1 |
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