IDT70V3319 datasheet, PDF - EEWORLD Datasheet

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IDT70V3319: Description256K X 18 DUAL-PORT SRAM, 15 ns, PQFP128; Categorystorage; File Size348KB，23 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT70V3319 Overview

256K X 18 DUAL-PORT SRAM, 15 ns, PQFP128

IDT70V3319 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	128
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	3.45 V
Minimum supply/operating voltage	3.15 V
Rated supply voltage	3.3 V
maximum access time	15 ns
Processing package description	14 X 20 MM, 1.40 MM HEIGHT, TQFP-128
state	ACTIVE
Craftsmanship	CMOS
packaging shape	RECTANGULAR
Package Size	FLATPACK, LOW PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	TIN LEAD
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	COMMERCIAL
memory width	18
organize	256K X 18
storage density	4.72E6 deg
operating mode	SYNCHRONOUS
Number of digits	262144 words
Number of digits	256K
Memory IC type	DUAL-PORT SRAM
serial parallel	PARALLEL

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HIGH-SPEED 3.3V

256/128K x 18

IDT70V3319/99S

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

– Industrial: 4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

– Due to limited pin count PL/

option is not supported

on the 128-pin TQFP package. Device is pipelined

outputs only on each port.

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 6ns cycle time, 166MHz operation (6Gbps bandwidth)

– Fast 3.6ns clock to data out

– 1.7ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 166MHz

◆

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output mode

LVTTL- compatible, single 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 133MHz.

Available in a 128-pin Thin Quad Flatpack, 208-pin fine

pitch Ball Grid Array, and 256-pin Ball

Grid Array

Supports JTAG features compliant to IEEE 1149.1

– Due to limited pin count, JTAG is not supported on the

128-pin TQFP package.

Functional Block Diagram

FT/PIPE

1/0

0a 1a

0b 1b

1b 0b

1a 0a

1/0

FT/PIPE

R/W

1/0

B B

1 0

R R

1/0

R/W

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

1b 0b 1a 0a

0a 1a 0b 1b

0/1

FT/PIPE

0/1

256K x 18

MEMORY

ARRAY

I/O

- I/O

17L

Din_L

Din_R

I/O

- I/O

17R

CLK

17L(1)

REPEAT

ADS

CNTEN

CLK

17R(1)

Counter/

Address

Reg.

ADDR_L

ADDR_R

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

5623 tbl 01

TDI

NOTE:

1. A

is a NC for IDT70V3399.

JTAG

TDO

TCK

TMS

TRST

MAY 2003

DSC 5623/7

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