LVCMOS Dual-Frequency Programmable
VCXO
IDT8N0DV85
DATA SHEET
General Description
The IDT8N0DV85 is a LVCMOS Dual-Frequency Programmable
VCXO with very flexible frequency and pull-range programming
capabilities. The device uses IDT’s fourth generation FemtoClock
®
NG technology for an optimum of high clock frequency and low
phase noise performance. The device accepts 2.5V or 3.3V supply
and is packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm
x 7mm x 1.55mm package.
The device can be factory-programmed to any two frequencies in the
range of 15.476MHz to 260MHz to the very high degree of frequency
precision of 218Hz or better. The output frequency is selected by the
FSEL pin. The extended temperature range supports wireless
infrastructure, telecommunication and networking end equipment
requirements.
Features
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Fourth generation FemtoClock
®
NG technology
Programmable clock output frequency from 15.476MHz to
260MHz
Two factory-programmed output frequencies
Frequency programming resolution is 218Hz and better
Absolute pull-range (APR) programmable from ±4.5 to
±754.5ppm
One 2.5V or 3.3V LVCMOS clock output
RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.65ps (typical)
RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.94ps (typical)
2.5V or 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm
package
Block Diagram
Pin Assignment
OSC
114.285 MHz
2
÷P
PFD
&
LPF
FemtoClock
®
NG
VCO
1950-2600MHz
VC 1
6 V
CC
5 DNU
4 Q
÷N
Q
FSEL 2
GND 3
÷MINT,
MFRAC
9
VC
Pulldown
A/D
25
Configuration Register (ROM)
(Frequency, Pull range, Polarity)
7
IDT8N0DV85
6-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
FSEL
IDT8N0DV85ACD REVISION A AUGUST 14, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N0DV85 Data Sheet
LVCMOS Dual-Frequency Programmable VCXO
Pin Description and Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
Name
VC
FSEL
GND
Q
DNU
V
CC
Power
Input
Input
Power
Output
Type
Description
VCXO Control Voltage input.
Pulldown
NOTE 1
Frequency select pin. See Table 3B for function. LVCMOS/LVTTL interface levels.
Power supply pin.
Clock output. LVCMOS interface levels.
Do not use.
Power supply pin.
NOTE 1.Pulldown refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
FSEL
VC
V
CC
= 3.465V or 2.625V
V
CC
= 3.3V
V
CC
= 2.5V
Test Conditions
Minimum
Typical
5.5
10
8
50
14
17
Maximum
Units
pF
pF
pF
k
Ω
Power Dissipation Capacitance
Input Pulldown Resistor
Output Impedance
Q
Ω
Ω
Function Tables
Table 3A. Output Frequency
15.476MHz to 260MHz
NOTE. Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of
218Hz.
IDT8N0DV85ACD REVISION A AUGUST 14, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N0DV85 Data Sheet
LVCMOS Dual-Frequency Programmable VCXO
Principles of Operation
The block diagram consists of the internal 3
RD
overtone crystal and
oscillator which provide the reference clock f
XTAL
of 114.285MHz.
The PLL includes the FemtoClock NG VCO along with the
Pre-divider (P), the feedback divider (M) and the post divider (N). The
P, M,
and
N
dividers determine the output frequency based on the
f
XTAL
reference. The feedback divider is fractional supporting a huge
number of output frequencies. Internal registers are used to hold up
to two different factory pre-set configuration settings. The
configuration is selected via the FSEL pin. Changing the FSEL
control results in an immediate change of the output frequency to the
selected register values. The
P, M,
and
N
frequency configurations
support an output frequency range 15.476MHz to 260MHz.
The devices use the fractional feedback divider with a delta-sigma
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator. The output frequency
is determined by the 2-bit pre-divider (P), the feedback divider (M)
and the 7-bit post divider (N). The feedback divider (M) consists of
both a 7-bit integer portion (MINT) and an 18-bit fractional portion
(MFRAC) and provides the means for high-resolution frequency
generation. The output frequency f
OUT
is calculated by:
1
MFRAC
+ 0.5
-
f OUT
=
f XTAL
⋅
------------
⋅
MINT
+
------------------------------------
P
⋅
N
18
2
Frequency Configuration
An order code is assigned to each frequency configuration and the
VCXO pull-range programmed by the factory (default frequencies).
For more information on the available default frequencies and order
codes, please see the Ordering Information Section in this document.
For available order codes, see the
FemtoClock NG Ceramic-Package
XO and VCXO Ordering Product Information
document.
For more information on programming capabilities of the device for
custom frequency and pull-range configurations, see the
FemtoClock
NG Ceramic 5x7 Module Programming Guide.
Table 3B. Frequency Selection
Input
FSEL
0 (default)
1
Selects
Frequency 0
Frequency 1
(1)
IDT8N0DV85ACD REVISION A AUGUST 14, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N0DV85 Data Sheet
LVCMOS Dual-Frequency Programmable VCXO
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
3.63V
-0.5V to V
CC
+ 0.5V
-0.5V to V
CC
+ 0.5V
49.4°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
CC
=
3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
CC
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
135
Maximum
3.465
163
Units
V
mA
Table 4B. Power Supply DC Characteristics, V
CC
=
2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
CC
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
124
Maximum
2.625
148
Units
V
mA
Table 4C. LVCMOS/LVTTL DC Characteristic, V
CC
=
3.3V ± 5% or V
CC
=
2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 2.5V
FSEL
FSEL
Q
Q
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
V
CC
= 3.465V
V
CC
= 2.625V
V
CC
= 3.465V or 2.625V
-5
2.6
1.8
0.6
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
V
V
V
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
IDT8N0DV85ACD REVISION A AUGUST 14, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N0DV85 Data Sheet
LVCMOS Dual-Frequency Programmable VCXO
AC Electrical Characteristics
Table 5A. VCXO Control Voltage Input (V
C
) Characterisitics, V
CC
= 3.3V ± 5% or 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
Parameter
Test Conditions
ADC_GAIN[5:0] = 000001
ADC_GAIN[5:0] = 000010
Oscillator Gain, NOTE 1, 2, 3
V
CC
= 3.3V
K
V
Oscillator Gain, NOTE 1, 2, 3
V
CC
= 2.5V
ADC_GAIN[5:0] = XXXXXX
ADC_GAIN[5:0] = 111110
ADC_GAIN[5:0] = 111111
ADC_GAIN[5:0] = 000001
ADC_GAIN[5:0] = 000010
ADC_GAIN[5:0] = XXXXXX
ADC_GAIN[5:0] = 111110
ADC_GAIN[5:0] = 111111
L
VC
BW
R
VC
VC
NOM
V
C
Control Voltage Linearity
Modulation Bandwidth
VC Input Resistance
Nominal Control Voltage
Control Voltage Tuning
Range; NOTE 4
0
500
V
CC
÷2
V
CC
BSL Variation; NOTE 4
-1
Minimum
Typical
7.57
15.15
25 · ADC_GAIN ÷ V
CC
469.69
477.27
10
20
25 · ADC_GAIN ÷ V
CC
620
630
±0.1
100
+1
Maximum
Units
ppm/V
ppm/V
ppm/V
ppm/V
ppm/V
ppm/V
ppm/V
ppm/V
ppm/V
ppm/V
%
kHz
kΩ
V
V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: V
C
= 10% to 90% of V
CC
.
NOTE 2: Nominal oscillator gain: Pull range divided by the control voltage tuning range of 3.3V.
E.g. for ADC_GAIN[6:0] = 000001 the pull range is ±12.5ppm, resulting in an oscillator gain of 25ppm ÷ 3.3V = 7.57ppm/V.
NOTE 3: For best phase noise performance, use the lowest K
V
that meets the requirements of the application.
NOTE 4: BSL = Best Straight Line Fit: Variation of the output frequency vs. control voltage V
C
, in percent. V
C
ranges from 10% to 90% V
CC
.
IDT8N0DV85ACD REVISION A AUGUST 14, 2012
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©2012 Integrated Device Technology, Inc.
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