EEWORLDEEWORLDEEWORLD

Part Number

Search

D3D5795T20303FG-G

Description
Parallel - Fundamental Quartz Crystal, 3.5795MHz Nom,
CategoryPassive components    Crystal/resonator   
File Size568KB,3 Pages
ManufacturerDB Lectro Inc
Environmental Compliance  
Download Datasheet Parametric View All

D3D5795T20303FG-G Overview

Parallel - Fundamental Quartz Crystal, 3.5795MHz Nom,

D3D5795T20303FG-G Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Objectid1351494768
Reach Compliance Codeunknown
Other featuresAT CUT; TR
Ageing3 PPM/FIRST YEAR
Crystal/Resonator TypePARALLEL - FUNDAMENTAL
Drive level10 µW
frequency stability0.003%
frequency tolerance30 ppm
load capacitance20 pF
Installation featuresSURFACE MOUNT
Nominal operating frequency3.5795 MHz
Maximum operating temperature70 °C
Minimum operating temperature-20 °C
Series resistance180 Ω
surface mountYES
Holder code C & D & F,
CYLINDER CRYSTAL
FEATURE
Wide Frequency range
High shock tolerance
Small size
Reliable frequency stability
Lead Free & RoHS Compliant
QUARTZ CRYSTAL UNIT
APPLICATIONS
Microprocessor Systems
Consumer Electronics
Instrumentation
Automotive electronics
Φ3
x 10
3.579MHz ~ 4.000MHz
Φ3
x 9 /Φ3 x 8
4.000MHz~50MHz
ELECTRICAL SPECIFICATIONS
Hold Type
Frequency
Oscillator mode
Frequency Tolerance (at 25°C)
ESR
Frequency Stability
Storage Temperature Range
Operating Temperature Range
Shunt Capacitance (C0)
Driver Level (Typical)
Load Capacitance(C
L
)
Insulation Resistance
Aging @25°C
1
st
year (Max)
3.579MHz ~ 50MHz
See Table
±10ppm, ±20ppm, ±30ppm or specify
See Table
See Table
-40
°C
to + 85
°C
-10
°C
to + 60
°C
°C
to +70
°C
20
°C
to +85
°C
40
5.0pF Typ
10 ~ 100 µW Max
12PF, 16PF, 18PF, 20PF or Specify
500MΩ AT DC100V Min
±3ppm/year
REMARK:
SPECIFICATIONS SUBJECT TO CHANGE WITHOUT PRIOR NOTICE. PLEASE CONFIRM
WITH OUR SALES ENGINEER.
EQUIVALENT SERIES RESISTANCE(ESR) AND OSCILLATION MODE
Frequency
Range
3.579MHz~3.999MHz
4.000MHz~4.499MHz
4.500MHz~4.999MHz
5.000MHz~6.999MHz
E.S.R
(
Ω)
180Max
150Max
120Max
100Max
Mode
Fundamental/AT
Fundamental/AT
Fundamental/AT
Fundamental/AT
Frequency Range
7.000MHz~9.999MHz
10.000MHz~11.999MHz
12.000MHz~29.999MHz
30.000MHz~50.000MHz
E.S.R
(
Ω)
80Max
60Max
40Max
80Max
Mode
Fundamental/AT
Fundamental/AT
Fundamental/AT
3rd Overtone /AT
DB Lectro Inc. 3755 Place Java, Suite 140, Brossard, Québec, J4Y 0E4, Canada - T: 1-450-444-1424 / F: 1-450-444-4714 / www.dblectro.com
The operator "===" or "!==" in Verilog cannot be synthesized
The operators "===" or "!==" in Verilog cannot be synthesized , but what should I do if I cannot modify them to "==" or "!="? I still want to synthesize successfully....
gjgd FPGA/CPLD
Please help, how to control those TFT screens that only have DE signal? (LCD DE mode)
For example: AT080TN42, the last useful signals are only DE, CLK and color signal. How does this TCON board tell when the frame starts? (There is no frame synchronization signal) Please give me some a...
blue670117 Embedded System
Cross-platform library for mobile device application development
Are you still worried about developing mobile device applications for different platforms? Use MUI!!! MUI is a cross-platform mobile device application development library. You can use the rich librar...
zms9439 Embedded System
【Power amplifier application】 Lamb wave signal analysis based on dry-coupled ultrasonic testing
The dry coupling ultrasonic testing method does not require the application of liquid coupling agents such as water or oil on the surface of the material to be tested. It is easy to operate and flexib...
aigtek01 Test/Measurement
Research on the design principles of human-machine interface of DCS system in power generation enterprises
Abstract: With the development of computer software, the design of human-machine interface has become increasingly complex, and the design principles have also undergone fundamental changes. This pape...
frozenviolet Industrial Control Electronics
How did you get the pinout table for the FPGA development board? Is it based on the schematic?
I use DE1-SoC, but I can't find the corresponding allocation table. There are some DE2 ones on the Internet. . ....
1696811157 FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2565  2416  1682  2667  559  52  49  34  54  12 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号