EEWORLDEEWORLDEEWORLD

Part Number

Search

FMXMC6S2106FKJ-08.000000M

Description
Parallel - Fundamental Quartz Crystal, 8MHz Nom, ROHS COMPLIANT, MINIATURE, CERAMIC, SMD, 2 PIN
CategoryPassive components    Crystal/resonator   
File Size198KB,1 Pages
ManufacturerFrequency Management International
Environmental Compliance
Download Datasheet Parametric View All

FMXMC6S2106FKJ-08.000000M Overview

Parallel - Fundamental Quartz Crystal, 8MHz Nom, ROHS COMPLIANT, MINIATURE, CERAMIC, SMD, 2 PIN

FMXMC6S2106FKJ-08.000000M Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid1315091375
package instructionROHS COMPLIANT, MINIATURE, CERAMIC, SMD, 2 PIN
Reach Compliance Codecompliant
Ageing5 PPM/YEAR
Crystal/Resonator TypePARALLEL - FUNDAMENTAL
Drive level10 µW
frequency stability0.01%
frequency tolerance20 ppm
load capacitance6 pF
Installation featuresSURFACE MOUNT
Nominal operating frequency8 MHz
Maximum operating temperature50 °C
Minimum operating temperature
physical sizeL6.0XB3.5XH1.1 (mm)/L0.236XB0.138XH0.043 (inch)
Series resistance60 Ω
surface mountYES
FMXMC6S2
SERIES
Microprocessor Crystals
Surface Mount Ceramic Pkg.
Miniature 2-Pad / Ultra Thin
High Reliability
Tight Stability
CERAMIC SMD 6x3.5
SPECIFICATIONS
Issue 2 | 07252012
Parameter
Frequency Range
Operation Mode
Load Capacitance (CL)
Frequency Tolerance
Temperature Tolerance
Operating Temperature
Storage Temperature
Equivalent Series Resistance (ESR)
Shunt Capacitance (C0)
Drive Level
Aging @ +25°C
Insulation Resistance
Reflow Conditions
All specifications subject to change without notice.
Specification
8 - 150 MHz
See Operation Mode and ESR Table
18 pF Std, 6 - 60 pF and Series available
±30 ppm @ 25°C Std (See Cal. Tol. for Options)
±50 ppm Std (See Temp. Tol. for Options)
0 to +70°C Std (See Temp. Range for Options)
-40 to +85°C / -55 to +125°C
See Operation Mode and ESR Table
7 pF max
10 µW typical, 300 µW max
±3 ppm typical; ±5 ppm per year max
500MΩ min at 100V
DC
±15V
+260ºC ±10ºC for 10 sec max 2 reflows max
6x3.5 CERAMIC SMD
OPERATION MODE AND ESR TABLE
Frequency (MHz)
8.0 - 13.9
14.0 - 39.0
40.0 - 150.0
Mode
Fundamental
Fundamental
3rd Overtone
Max. ESR (Ohms)
60
40
80
STANDARD MARKING
XXX.XXXM
XXXXXXX
FMI YYWW
XXX.XXXM FREQUENCY in MHz
XXXXXXX Part Number
FMI, Date Code
Recommended Solder Pad Layout
NOTE: Standard Specifications for product indicated in
color
Dimensions:
Inches
(mm)
PART DESCRIPTION SYSTEM
MARKING: See Page 52, Format A
FMXM C6S2 1 18 H J A - XX.XXXXXXM - CM
Product Family
MicroP Crystal
Package
Ceramic SMD
6x3.5mm, 2 pad
Mode
1 - Fundamental
3 - 3rd Overtone
Load Cap. (CL)
18 - Standard (pF)
00 - Series
XX - Custom (pF)
Cal. Tol. @ 25°C
D ±10 ppm
F ±20 ppm
H ±30 ppm
J ±50 ppm
K ±100 ppm
X Custom
Frequency (MHz)
Temp. Range
A 0 to 70 °C
B -20 to 70 °C
C -40 to 85 °C
D -10 to 50 °C
E -10 to 60 °C
F -30 to 60 °C
J 0 to 50 °C
X Custom
Options
TR - Tape & Reel
PD - Parameter Data
TD - Temp. Data
TG - Temp. Grading
CM - Custom Mark
BLANK - None Req’d.
Temp. Tol.
D ±10 ppm
F ±20 ppm
H ±30 ppm
J ±50 ppm
K ±100 ppm
X Custom
1-800-800-XTAL
[9825]
www.fmi-inc.com
15
power supply
Can a 1.5V dry cell and two capacitors produce a short-term 3V voltage?...
芯风作浪 Power technology
How to write a Camera application based on DirectShow technology under WINCE60? Just like the camera application made on PC through DirectShow technology, it can browse and take pictures
How to write a Camera application based on DirectShow technology under WINCE60? Just like the camera application made on PC through DirectShow technology, it can browse and take pictures....
5151515151 Embedded System
Arrow Electronics' award-winning live broadcast starts at 10:00 this morning: Intel FPGA Deep Learning Acceleration Technology
Arrow Electronics' award-winning live broadcast starts at 10:00 this morning: Intel FPGA Deep Learning Acceleration TechnologyClick here to enter the live broadcastLive broadcast time: 10:00-11:30 am,...
EEWORLD社区 FPGA/CPLD
What are the development software of Xilinx?
Dear experts, I would like to ask, what are the software for developing Xilinx? Do they have commands to keep the specified reg from being optimized? ?...
eeleader FPGA/CPLD
Schematic diagram - How does this circuit achieve the self-locking function of the switch?
[i=s]This post was last edited by Plakatu on 2022-3-4 09:08[/i]The circuit is as shown above. Note: The switch is a touch switch and has no self-locking function. *************************************...
普拉卡图 Analog electronics
Power group matching table
[i=s] This post was last edited by dontium on 2015-1-23 13:24 [/i] Resistance matching table...
linming123 Analogue and Mixed Signal

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 832  1097  941  1091  244  17  23  19  22  5 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号