ADS1245
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
Low-Power, 24-Bit
Analog-to-Digital Converter
FEATURES
D
D
D
D
D
D
D
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D
D
D
D
D
D
D
20-Bit Effective Resolution
High-Impedance Buffered Input
±2.5V
Differential Input Range
Pin-Compatible with ADS1244
0.0006% INL (typ), 0.0015% INL (max)
Simple Two-Wire Serial Interface
Simultaneous 50Hz and 60Hz Rejection
Single Conversions with Sleep Mode
Single-Cycle Settling
Self-Calibration
Well Suited for Multi-Channel Systems
Easily Connects to the MSP430
Current Consumption: 158µA
Analog Supply: 2.5V to 5.25V
Digital Supply: 1.8V to 3.6V
DESCRIPTION
The ADS1245 is a 24-bit, delta-sigma analog-to-digital
converter (ADC). It offers excellent performance and very
low power in an MSOP-10 package and is well suited for
demanding high-resolution measurements, especially in
portable and other space- and power-constrained
systems.
The buffered input presents an impedance of 3GΩ, mini-
mizing measurement errors when using high-impedance
sources. The ADS1245 is compatible with ADS1244 and
offers a direct upgrade path for designs requiring higher in-
put impedance.
A third-order delta-sigma (∆Σ) modulator and digital filter
form the basis of the ADC. The analog modulator has a
±2.5V
differential input range. The digital filter rejects both
50Hz and 60Hz signals, completely settles in one cycle,
and outputs data at 15 samples per second (SPS).
A simple, two-wire serial interface provides all the
necessary control. Data retrieval, self-calibration, and
Sleep mode are handled with a few simple waveforms.
When only single conversions are needed, the ADS1245
can be shut down (Sleep mode) while idle between
measurements to dramatically reduce the overall power
dissipation. Multiple ADS1245s can be connected
together to create a synchronously sampling multichannel
measurement system. The ADS1245 is designed to easily
connect to microcontrollers, such as the MSP430.
The ADS1245 supports 2.5V to 5.25V analog supplies and
1.8V to 3.6V digital supplies. Power is typically less than
470µW in normal operation and less than 1µW during
Sleep mode.
VREFP VREFN
AVDD
DVDD
APPLICATIONS
D
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Hand-Held Instrumentation
Portable Medical Equipment
Industrial Process Control
Test and Measurement Systems
CLK
DRDY/DOUT
Buffer
AINN
3rd−
Order
Modulator
Digital
Filter
Serial
Interface
SCLK
AINP
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
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ADS1245
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
www.ti.com
ORDERING INFORMATION
PRODUCT
PACKAGE−LEAD
PACKAGE
DESIGNATOR(1)
DGS
SPECIFIED
TEMPERATURE
RANGE
−40°C to +85°C
PACKAGE
MARKING
BHI
ORDERING
NUMBER
ADS1245IDGST
ADS1245
MSOP-10
ADS1245IDGSR
(1) For the most current specifications and package information, refer to our web site at www.ti.com.
TRANSPORT
MEDIA, QUANTITY
Tape and Reel, 250
Tape and Reel, 2500
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
ADS1245
AVDD to GND
DVDD to GND
Input Current
Input Current
Analog Input Voltage to GND
Analog Input Voltage to GND
Digital Output Voltage to GND
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
−0.3 to +6
−0.3 to +3.6
100, momentary
10, continuous
−0.5 to AVDD + 0.5
−0.3 to DVDD + 0.3
−0.3 to DVDD + 0.3
+150
−40 to +85
−60 to +150
UNIT
V
V
mA
mA
V
V
V
°C
°C
°C
PIN ASSIGNMENTS
DGS PACKAGE
MSOP
(TOP VIEW)
ADS1245
GND
VREFP
VREFN
AINN
AINP
1
2
3
4
5
10
9
8
7
6
CLK
SCLK
DRDY/DOUT
DVDD
AVDD
Lead Temperature (soldering, 10s)
+300
°C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
TERMINAL
NAME
GND
VREFP
VREFN
AINN
AINP
AVDD
DVDD
DRDY/DOUT
Terminal Functions
NO.
1
2
3
4
5
6
7
8
DESCRIPTION
Analog and digital ground
Positive reference input
Negative reference input
Negative analog input
Positive analog input
Analog power supply, 2.5V to 5.25V
Digital power supply, 1.8V to 3.6V
Dual-purpose output:
Data ready: indicates valid data by going low.
Data output: outputs data, MSB first, on the
first rising edge of SCLK.
Serial clock input: clocks out data on the
rising edge. Used to initiate calibration and
Sleep mode (see text for more details).
System clock input: typically 2.4576MHz
SCLK
9
CLK
10
2
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ADS1245
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
ELECTRICAL CHARACTERISTICS
All specifications at TA = −40°C to +85°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +1.25V, unless otherwise noted.
PARAMETER
Analog Input
Full-scale input voltage range
Absolute input range
Differential input impedance
System Performance
Resolution
Data rate
Integral nonlinearity (INL)
Offset error
Offset error drift(3)
Gain error(4)
Gain error drift(3)
Common-mode rejection
TEST CONDITIONS
AINP − AINN
AINP, AINN with respect to GND
fCLK = 2.4576MHz
No missing codes
fCLK = 2.4576MHz
Differential input signal, end point fit
MIN
TYP
±2V
REF
GND + 0.1
3
24
15
±0.0006
1
0.01
0.005
0.5
100
±0.0015
14
0.1
AVDD − 1.25
MAX
UNIT
V
V
GΩ
Bits
SPS(1)
%FSR
(2)
ppm of FSR
ppm of FSR/°C
%
Normal-mode rejection
Input referred noise
Analog power-supply rejection
Digital power-supply rejection
Voltage Reference Input
Reference input voltage (VREF)
Negative reference input (VREFN)
Positive reference input (VREFP)
Voltage reference impedance
Digital Input/Output
VIH (CLK, SCLK)
VIL (CLK, SCLK)
Logic levels
VOH (DRDY, DOUT)
VOL (DRDY, DOUT)
Input leakage (CLK, SCLK)
CLK frequency (fCLK)
CLK duty cycle
Power Supply
AVDD
DVDD
AVDD current
At DC
fCM(5) = 50
±
1Hz, fCLK = 2.4576MHz
fCM = 60
±
1Hz, fCLK = 2.4576MHz
fSIG(6) = 50
±
1Hz, fCLK = 2.4576MHz
fSIG = 60
±
1Hz, fCLK = 2.4576MHz
90
100
100
60
70
2
At DC,
∆AVDD
= 5%
At DC,
∆AVDD
= 5%
VREF
≡
VREFP − VREFN
0.5
GND − 0.1
VREFN + 0.5
100
100
1.25
AVDD(7)
VREFP − 0.5
AVDD + 0.1
ppm/°C
dB
dB
dB
dB
dB
ppm of FSR,
RMS
dB
dB
V
V
V
MΩ
V
V
V
V
µA
fCLK = 2.4576MHz
0.8 DVDD
GND
DVDD − 0.4
GND
1
5.25
0.2 DVDD
DVDD
DVDD + 0.4
±10
6
70
5.25
3.6
1
250
5
10
IOH = 1mA
IOL = 1mA
0 < (CLK, SCLK) < DVDD
30
2.7
1.8
Sleep mode
AVDD = 3V
AVDD = 5V
Sleep mode, CLK stopped
Sleep mode, 2.4576MHZ CLK running
DVDD = 3V
AVDD = DVDD = 3V
0.1
152
158
0.1
1.6
5
0.47
MHz
%
V
V
µA
µA
µA
µA
µA
µA
DVDD current
Total power dissipation
mW
(1) SPS = samples per second.
(2) FSR = full-scale range = 4VREF.
(3) Recalibration can reduce these errors to the level of the noise.
(4) Achieving specified gain error performance requires that calibration be performed with reference voltage input between (GND + 0.1V) and
(AVDD − 1.25V). See
Voltage Reference Inputs
section.
(5) fCM is the frequency of the common-mode input.
(6) fSIG is the frequency of the input signal.
(7) It will not be possible to reach the digital output full-scale code when VIN > 2VREF.
3
ADS1245
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +1.25V, unless otherwise specified.
ANALOG CURRENT vs TEMPERATURE
220
210
200
190
Current (
µ
A)
170
160
150
140
130
120
110
100
0
−45
−25
−5
15
35
55
75
95
−45
2
AVDD = +3V, f
CLK
= 2.4576MHz
Current (µA)
180
AVDD = +5V, f
CLK
= 4.9152MHz
8
6
4
12
10
DIGITAL CURRENT vs TEMPERATURE
DVDD = +3V, f
CLK
= 4.9152MHz
DVDD = +1.8V, f
CLK
= 2.4576MHz
−25
−5
15
35
55
75
95
Temperature (
_
C)
Temperature (
_
C)
Figure 1
ANALOG CURRENT vs ANALOG SUPPLY
164
162
160
Current (µA)
Current (µA)
158
156
154
152
150
148
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Analog Supply (V)
f
CLK
= 2.4576MHz
f
CLK
= 4.9152Hz
16
14
12
10
8
6
4
2
0
−
45
−
25
−
5
Figure 2
DIGITAL CURRENT vs DIGITAL SUPPLY
f
CLK
= 4.9152MHz
f
CLK
= 2.4576MHz
15
35
55
75
95
Digital Supply (V)
Figure 3
INTEGRAL NONLINEARITY vs ANALOG SUPPLY
V
REF
= 1.25; f
OSC
= 2.4576MHz
V
CM
= 2.4 or (( AVDD
−
1.8)/2 + 0.3), whichever is smaller
30
25
INL (ppm of FSR)
INL (ppm of FSR)
20
15
10
5
T = +85_ C
0
2.5
3.0
3.5
4.0
AVDD (V)
4.5
5.0
5.5
12.5
10.0
7.5
5.0
2.5
0
−2.5
−5.0
−7.5
−10.0
−12.5
−2.5
−1.5
T =
−
40_C
Figure 4
INTEGRAL NONLINEARITY vs V
IN
T = +25_C
T = +85_ C
T = +25_ C
T =
−40_C
−0.5
V
IN
(V)
0.5
1.5
2.5
Figure 5
4
Figure 6
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ADS1245
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +1.25V, unless otherwise specified.
OFFSET vs TEMPERATURE
5
Normalized Offset (ppm of FSR)
4
3
Gain (Normalized)
2
1
0
−
1
−2
−3
−4
−5
−45
−25
−5
15
35
55
75
95
1.00006
1.00005
1.00004
1.00003
1.00002
1.00001
1.00000
0.99999
0.99998
0.99997
0.99996
0.99995
0.99994
GAIN vs TEMPERATURE
Temperature (
_
C)
−45
−25
−5
15
35
55
75
95
Temperature (_ C)
Figure 7
NOISE vs INPUT SIGNAL
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
−
2.5
0
−
1.5
−
0.5
V
IN
(V)
0.5
1.5
2.5
−45
−25
−5
Noise (ppm of FSR, RMS)
Noise (ppm of FSR, RMS)
2.5
2.0
1.5
1.0
0.5
3.0
Figure 8
NOISE vs TEMPERATURE
15
35
55
75
95
Temperature (
_
C)
Figure 9
HISTOGRAM OF OUTPUT DATA
900
160
800
Number of Occurences
700
600
CMRR (dB)
500
400
300
200
100
0
−14
−12
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
1
2
3
4
5
6
7
8
9
10
11
12
0
1
10
140
120
100
80
60
40
20
Figure 10
COMMON−
MODE REJECTION RATIO
vs FREQUENCY
100
1k
10k
100k
ppm of FSR
Frequency (Hz)
Figure 11
Figure 12
5
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