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Q33210BG0002801

Description
CMOS Output Clock Oscillator,
CategoryPassive components    oscillator   
File Size269KB,5 Pages
ManufacturerSeiko Epson Corporation
Download Datasheet Parametric View All

Q33210BG0002801 Overview

CMOS Output Clock Oscillator,

Q33210BG0002801 Parametric

Parameter NameAttribute value
Objectid8355250973
Reach Compliance Codeunknown
Other featuresSTANDBY; ENABLE/DISABLE FUNCTION; TAPE
maximum descent time5 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
Installation featuresSURFACE MOUNT
Nominal operating frequency16 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS
Output load15 pF
physical size2.5mm x 2.0mm x 0.8mm
longest rise time5 ns
Maximum supply voltage1.7 V
Minimum supply voltage1.3 V
Nominal supply voltage1.5 V
surface mountYES
maximum symmetry55/45 %
Clock OSC
SG-210SGB
SG-210SGB 16.000000 MHz L
Product name
Product Number / Ordering code
Q33210BG00028xx
Please refer to the 8.Packing information about xx (last 2 digits)
Output waveform CMOS
Pb free / Complies with EU RoHS directive
Reference weight Typ. 15 mg
1.Absolute maximum ratings
Parameter
Symbol
Maximum supply voltage
Storage temperature
Input voltage
Min.
-0.3
-40
-0.3
Typ.
-
-
-
Max.
5
125
Vcc+0.3
Unit
V
ºC
V
Conditions / Remarks
-
Storage as single product
ST terminal
Vcc-GND
T_stg
Vin
2.Specifications(characteristics)
Parameter
Symbol
Output frequency
Supply voltage
Operating temperature
Frequency tolerance
Current consumption
Stand-by current
Symmetry
Output voltage
Output load condition
Input voltage
Rise time
Fall time
Start-up time
Jitter
Min.
1.3
-40
-50
-
-
45
0.9Vcc
-
-
0.8Vcc
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-3
-
Typ.
16.0000
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
-
-
Max.
1.7
85
50
1
0.3
55
-
0.1Vcc
15
-
0.2Vcc
5
5
3
-
-
-
-
-
-
-
-
-
-
-
-
-
3
-
Unit
MHz
V
ºC
x10
-6
mA
µA
%
Conditions / Remarks
-
-
T_use
No load condition
ST = GND
50% Vcc Level L_CMOS=<15pF
IOH=-1mA
IOL=1mA
f0
Vcc
T_use
f_tol
Icc
I_std
SYM
V
OH
V
OL
L_CMOS
V
IH
V
IL
t
r
tf
t_str
t
DJ
T
RJ
t
RMS
t
p-p
t
acc
pF
CMOS Load
ST terminal
ST terminal
ns
ns
ms
ps
ps
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
x10
-6
0.2Vcc to 0.8Vcc Level, L_CMOS=15pF
0.2Vcc to 0.8Vcc Level, L_CMOS=15pF
t = 0 at 0.9Vcc
Deterministic Jitter
Random Jitter
δ(RMS of total distribution)
Peak to Peak
Accumulated Jitter(δ) n=2 to 50000
cycles
Off set Frequency: 12kHz to 20MHz
Off set 1Hz
Off set 10Hz
Off set 100Hz
Off set 1kHz
Off set 10kHz
Off set 100kHz
Off set 1MHz
@+25ºC first year
-
Phase jitter
Phase noise
t
PJ
L(f)
Frequency aging
f_age
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