Z85C3010VSC datasheet, PDF - EEWORLD Datasheet

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Z85C3010VSC: Description2 CHANNEL(S), 4.1M bps, MULTI PROTOCOL CONTROLLER, PQCC44; CategoryThe embedded processor and controller Microcontrollers and processors; File Size631KB，2 Pages; ManufacturerZilog, Inc.; Websitehttps://www.zilog.com/

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Z85C3010VSC Overview

2 CHANNEL(S), 4.1M bps, MULTI PROTOCOL CONTROLLER, PQCC44

Z85C3010VSC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Zilog, Inc.
Objectid	1439907632
Parts packaging code	LCC
package instruction	QCCJ, LDCC44,.7SQ
Contacts	44
Reach Compliance Code	unknow
compound_id	884780
Other features	TWO MODEM CONTROL I/OS USABLE AS GENERAL PURPOSE I/OS; 10 X 19 FRAME STATUS FIFO
Address bus width	1
boundary scan	NO
Bus compatibility	Z80
maximum clock frequency	10 MHz
letter of agreement	ASYNC, BIT; SYNC, BYTE; SYNC, HDLC; SYNC, SDLC; X.25; BISYNC; EXT SYNC
Data encoding/decoding methods	NRZ; NRZI-SPACE; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.5125 MBps
External data bus width	8
JESD-30 code	S-PQCC-J44
JESD-609 code	e0
length	16.5862 mm
low power mode	NO
Number of DMA channels
Number of I/O lines
Number of serial I/Os	2
Number of terminals	44
On-chip data RAM width
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
RAM (number of words)	0
Maximum seat height	4.57 mm
Maximum slew rate	12 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	16.5862 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, MULTI PROTOCOL

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ZiLOG’s Family of

Serial Communication Controllers

SCC

8-bit Features include:

• Dual full-duplex channels (Z80230/Z85C30/Z85230)

• Single full-duplex channel (Z85233)

• Ability to accommodate a crystal oscillator, baud

rate generator, and digital phase-locked loop on

each channel

• Processing speeds up to 5Mbps

• Multi-protocol format (async, monosync, bisync,

ZiLOG Sets the standards for SCCs

For over 20 years ZiLOG has set the standard for

Serial Communication Controllers. Based on the

industry acclaimed SCC core, ZiLOG offers a wide

variety of Serial Communication Controllers to meet

your application requirements.

SDLC/HDLC, SDLC/HDLC loop)

• Encodes in the follow modes: NRZI, FM0, FM1

and Manchester

• CRC-16 or CRC-CCITT error detection

• 4-byte Transmit FIFO/8-byte Receive FIFO

(Z80230/Z85230/Z85233)

• 1-byte transmit FIFO/3-byte receive FIFO (Z85C30)

Reduces the need for external logic

ZiLOG SCCs offer low power consumption, higher

performance, and superior noise immunity. The many

on-chip features offered in ZiLOG SCCs help dramatically

to reduce the need for external logic and code develop-

ment found in most of the competition.

16-bit Solutions

The standard and integrated universal serial controllers,

Z16C30 and the Z16C32 offer 16-bit performance, with

processing speeds up to 20 Mbps.

16-bit Features include:

• Single (Z16C32) and dual (Z16C30)

full-duplex channels

• Accommodates two baud rate generators

and one digital phase-locked loop

• Processing speeds up to 10Mbps (Z16C30)

and 20Mbps (Z16C32)

• Multi-protocol format (async, monosync,

slaved monosync, bisync, isochronous,

nine-bit, SDLC/HDLC, SDLC/HDLC loop)

(additional 16-bit features on back)

8-bit Solutions

The standard serial and integrated communications

controller, Z85C30, allows you to easily implement a fully

integrated solution for many networking applications.

The enhanced dual and mono SCCs, the Z80230, Z85230

and the Z85233, include many features that make pro-

gramming easy. These parts also reduce CPU overhead,

allowing the programmer to select packet handling

response and improve cycle access recovery time.

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