ICS556-03
Q
UAD
LVDS O
SCILLATOR
/B
UFFER
Description
The ICS556-03 is a clock oscillator with quad LVDS
outputs. Using a standard 25 MHz crystal, no additional
external components are required to generate quad
LVDS outputs at 25 MHz.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
Features
•
•
•
•
•
•
Packaged in 16-pin TSSOP
Requires no external components
Low Phase Jitter: <1ps from 10 kHz to 10 MHz
Quad, Differential LVDS outputs
Operating voltage of 2.5 Volt
Advanced, low-power, sub-micron CMOS process
Block Diagram
VDD
EN1
EN2
EN3
EN4
CLKA
CLKA
CLKB
25MHz
Crystal
Oscillator
CLKB
CLKC
CLKC
CLKD
CLKD
LVDS
GND
MDS 556-03 B
I n t e gra te d C i r c u i t S y s t e m s
●
1
525 Race Stre et, San Jo se, CA 9 5126
●
Revision 030204
te l (40 8) 2 97-12 01
●
w w w. i c st . c o m
ICS556-03
Quad LVDS Oscillator/Buffer
Pin Assignment
EN1
VDD
A
A
B
B
EN2
X2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EN4
EN3
D
D
C
C
GND
X1
16-Pin (150 mil) SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
Pin
Name
EN1
VDD
A
A
B
B
EN2
X2
X1
GND
C
C
D
Pin
Type
Input
Power
Output
Output
Output
Output
Input
Input
Input
Power
Output
Output
Output
Pin Description
Enable pin for Outputs A and A. EN1 high enables A, A outputs.
EN1 low tri states A, A outputs. No Pull-Up resistor.
Power supply. Connect to 2.5 V.
Differential clock output.
Inverting differential clock output.
Inverting differential clock output.
Differential clock output.
Enable pin for Outputs B and B. EN2 high enables B, B outputs.
EN2 low tri states B, B outputs. No Pull-Up resistor.
Crystal connection.
Crystal input.
Connect to ground.
Differential clock output.
Inverting differential clock output.
Inverting differential clock output.
MDS 556-03 B
In te grated Circuit Systems
●
2
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 030204
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS556-03
Quad LVDS Oscillator/Buffer
Pin
Number
14
15
Pin
Name
D
EN3
Pin
Type
Output
Input
Differential clock output.
Pin Description
Enable pin for Outputs C and C. EN4 high enables C, C outputs.
EN3 low tri states C, C outputs.No Pull-Up resistor.
Enable pin for Outputs D and D. EN4 high enables D, D outputs.
EN4 low tri states D, D outputs.No Pull-Up resistor.
16
EN4
Input
External Component Selection
The ICS556-03 requires a minimum number of external
components for proper operation.
Quartz Crystal
The ICS556-03, a quad 25 MHz LVDS Clock utilizes an
external crystal to generate 4 pairs of low phase noise
outputs. The crystal should be a fundamental mode,
parallel resonant. Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these
capacitors is given by the following equation
Crystal Caps (pf)= (C
L
-12)x2
In the equation, CL is the crystal Load capacitance. So
for the crystal with 16pF load capacitance, two 8
pF[(16-12)x2] capacitors should be used.
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the ICS556-03. There should be no via’s
between the crystal pins and the X1 and X2 device
pins. There should be no signal traces underneath or
close to the crystal.
Decoupling Capacitors
A decoupling capacitor of 0.01µF should be connected
between VDD and GND on pins 2 and 10 as close to
the ICS556-03 possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
LVDS Driver Termination
A general LVDS interface is shown in Figure 2. In a 100
ohm differential transmission line environment, LVDS
drivers require a matched load termination of 100
across near the receiver input. For a multiple LVDS
outputs buffer, if only partial outputs are used, it is
recommended to terminate the un-used outputs.
2.5V
LVDS_Driver
2.5V
R1
100 ohm
+
-
100 Ohm Differential Transmission Line
Figure 2. Typical LVDS Driver
Termination
MDS 556-03 B
In te grated Circuit Systems
●
3
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 030204
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS556-03
Quad LVDS Oscillator/Buffer
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS556-03. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70°C
-65 to +150°C
260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Reference crystal parameters
Min.
0
+2.375
Typ.
Max.
+70
+2.625
Units
°C
V
Refer to page 3
MDS 556-03 B
In te grated Circuit Systems
●
4
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 030204
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS556-03
Quad LVDS Oscillator/Buffer
DC Electrical Characteristics
VDD=2.5 V ±5%
, Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Operating Voltage
Output High Voltage
Output Low Voltage
Input High Voltage (EN1,
EN2,EN3 & EN4)
Input High Voltage (EN1,
EN2,EN3 & EN4)
Operating Supply Current
Short Circuit Current
Symbol
VDD
V
OH
V
OL
V
IH
V
IL
IDD
I
OS
Conditions
Note 1
Note 1
Min.
2.375
1.375
Typ.
Max.
2.625
1.125
Units
V
V
V
V
2.0
0.5
OE1:4:1
OE1:4:0
17
4
±50
V
mA
mA
mA
Note 1: Outputs terminated with 50Ω to VDD/2
AC Electrical Characteristics
VDD = 2.5 V ±5%,
Ambient Temperature 0 to +70° C, CL=5 pF, unless stated otherwise
Parameter
Input Frequency
Output Frequency
Differential Output Voltages (V
OD
)
∆
V
OD
Offset Voltage (V
OS
)
∆
V
OS
Differential Output Short Circuit Current (I
OSD
)
Output Short Circuit Current (I
OS
)
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Output Short Circuit Current
Channel Output to output Skew
Part to Part Skew
Maximum Output Jitter (p-p)
Phase Jitter (RMS)
Conditions
Min.
Typ.
25
25
Max. Units
MHz
MHz
450
40
1.375
25
mV
mV
V
mV
mA
mA
1.2
1.2
55
100
1.5
ns
ns
%
mA
ps
ns
ps
1.0
ps
250
V
OD
Magnitude Change
V
OS
Magnitude Change
-40
1.125
350
0
1.25
3
-3.5
-3.5
20% to 80%, no load
20% to 80%, no load
Measured at 1.25V,
45
0.8
0.8
50
±50
20
40
Phase Noise integrated
from 10 kHz to 10 MHz
2
MDS 556-03 B
In te grated Circuit Systems
●
5
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 030204
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
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