HD74AC393
Dual Modulo-16-Counter
Description
The HD74AC393 contains a pair of high speed 4-stage ripple counters. Each half of the HD74AC393
operates as a modulo-16 binary divider, with the last three stages triggered in a ripple fashion. The flip-
flops are triggered by a High-to-Low transition of their
CP
inputs. Each half of each circuit type has a
Master Reset input which responds to a High signal by forcing all four outputs to the Low state.
Feature
•
Outputs Source/Sink 24 mA
Pin Arrangement
CP
1
MR 2
Q
0
3
Q
1
4
Q
2
5
Q
3
6
GND 7
(Top view)
14 V
CC
13
CP
12 MR
11 Q
0
10 Q
1
9 Q
2
8 Q
3
HD74AC393
Logic Symbol
(each half)
1, 13
CP
MR
Q
0
Q
1
Q
2
Q
3
2, 12
3, 11
4, 10
5, 9
6, 8
Vcc=Pin14
GND=Pin7
Pin Names
CP
MR
Q
0
– Q
3
Clock Pulse Input (Active Falling Edge)
Asynchronous Master Reset Input (Active High)
Flip-flop Outputs
Functional Description
Each half of the HD74AC393 operates in the modulo-16 binary sequence, as indicated in the + 16 Truth
Table. The first flip-flop is triggered by High-to-Low transitions of the
CP
input signal. Each of the other
flip-flops is triggered by a High-to-Low transition of the Q output of the preceding flip-flop. Thus state
changes of the Q outputs do not occur simultaneously. This means that logic signals derived from
combinations of these outputs will be subject to decoding spikes and, therefore, should not be used as
clocks for other counters, registers or flip-flops. A High signal on MR forces all outputs to the Low state
and prevents counting.
2
HD74AC393
Truth Table
Outputs
Count
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H :
L :
Q
3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
High Voltage Level
Low Voltage Level
Q
2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
Q
1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
Q
0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Logic Diagram
(one, half shown)
CP
K
C
D
Q
MR
Q
0
Q
1
Q
2
Q
3
CP
J
K
C
D
Q
CP
J
K
C
D
Q
CP
J
K
C
D
Q
CP
J
3
HD74AC393
DC Characteristics
(unless otherwise specified)
Item
Maximum quiescent supply current
Maximum quiescent supply current
Symbol
I
CC
I
CC
Max
80
8.0
Unit
µA
µA
Condition
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = Worst case
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = 25°C
AC Characteristics: HD74AC393
Ta = +25°C
C
L
= 50 pF
Item
Maximum clock
frequency
Propagation delay
CP
to Q
0
Propagation delay
CP
to Q
0
Propagation delay
CP
to Q
1
Propagation delay
CP
to Q
1
Propagation delay
CP
to Q
2
Propagation delay
CP
to Q
2
Propagation delay
CP
to Q
3
Propagation delay
CP
to Q
3
Propagation delay
MR to Q
0
, Q
1
, Q
2
or Q
3
Note:
t
PHL
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
Symbol
f
max
V
CC
(V)*
1
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Min
125
150
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Typ
—
—
8.5
6.5
8.0
6.0
12.0
9.5
11.5
9.0
15.0
12.0
14.5
11.5
18.0
14.5
17.5
14.0
10.5
8.5
Max
—
—
12.0
9.0
11.5
8.5
15.0
12.0
14.5
11.5
18.0
14.5
17.5
14.0
20.5
17.0
20.0
16.5
14.0
11.0
Ta = –40°C to +85°C
C
L
= 50 pF
Min
100
125
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
—
—
13.0
10.0
12.5
9.5
16.0
13.0
15.5
12.5
19.5
16.0
19.0
15.5
22.0
18.5
21.5
17.5
15.0
12.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
MHz
1. Voltage Range 3.3 is 3.3 V
±
0.3 V
Voltage Range 5.0 is 5.0 V
±
0.5 V
4
HD74AC393
AC Operating Requirements: HD74AC393
Ta = +25°C
C
L
= 50 pF
Item
Pulse width
CP
Recovery time MR to
CP
Note:
Symbol
t
w
V
CC
(V)*
1
Typ
3.3
5.0
t
rec
3.3
5.0
1. Voltage Range 3.3 is 3.3 V
±
0.3 V
Voltage Range 5.0 is 5.0 V
±
0.5 V
3.5
2.5
–2.5
–2.5
Ta = –40°C
to +85°C
C
L
= 50 pF
Guaranteed Minimum
5.5
4.5
0.0
0.0
7.0
5.0
0.0
0.0
ns
Unit
ns
Capacitance
Item
Input capacitance
Power dissipation capacitance
Symbol
C
IN
C
PD
Typ
4.5
50
Unit
pF
pF
Condition
V
CC
= 5.5 V
V
CC
= 5.0 V
5
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