SIT5146ACCFA230JRB1.000000X datasheet, PDF

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SIT5146ACCFA230JRB1.000000X: DescriptionClipped Sine Output Oscillator, 1MHz Nom,; CategoryPassive components oscillator; File Size2MB，36 Pages; ManufacturerSiTime; Environmental Compliance

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SIT5146ACCFA230JRB1.000000X Overview

Clipped Sine Output Oscillator, 1MHz Nom,

SIT5146ACCFA230JRB1.000000X Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	145142199297
package instruction	LCC10,.13X.2,58/52/48
Reach Compliance Code	unknown
Ageing	1 PPM/YEAR
maximum descent time	1.9 ns
Frequency Adjustment - Mechanical	NO
frequency stability	1%
Installation features	SURFACE MOUNT
Number of terminals	10
Nominal operating frequency	1 MHz
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
Oscillator type	CLIPPED SINE
Output impedance	17 Ω
Output level	0.8 V
Output load	15 pF
Package body material	CERAMIC
Encapsulate equivalent code	LCC10,.13X.2,58/52/48
physical size	5.15mm x 3.35mm x 1.06mm
longest rise time	1.9 ns
Maximum supply voltage	3.3 V
Minimum supply voltage	2.7 V
Nominal supply voltage	3 V
surface mount	YES
maximum symmetry	55/45 %

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SiT5146

Description

1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Endura™ Series Super-TCXO

Features



The

SiT5146

is a ruggedized ±0.5 to ±2.5 ppm MEMS

Super-TCXO with a maximum acceleration sensitivity of

0.009 ppb/g or 0.1 ppb/g. Engineered for best dynamic

performance, it is ideal for high reliability telecom, wireless

and networking, industrial, precision GNSS and

audio/video applications.

Leveraging SiTime’s unique DualMEMS

temperature

sensing and TurboCompensation

technologies, the

SiT5146 delivers the best dynamic performance for timing

stability in the presence of environmental stressors such as

air flow, temperature perturbation, vibration, shock, and

electromagnetic interference. This device also integrates

multiple on-chip regulators to filter power supply noise,

eliminating the need for a dedicated external LDO.

The SiT5146 offers three device configurations that can be

ordered using

Ordering Codes

for:

1) TCXO with non-pullable output frequency,

2) VCTCXO allowing voltage control of output frequency,

3) DCTCXO enabling digital control of output frequency

using an I

C interface, pullable to 5 ppt (parts per

trillion) resolution.

The SiT5146 can be factory programmed for any

combination of frequency, stability, voltage, and pull range.

Programmability enables designers to optimize clock

configurations while eliminating long lead times and

customization costs associated with quartz devices where

each frequency is custom built.

Refer to

Manufacturing Guideline

for proper reflow profile

and PCB cleaning recommendations to ensure best

performance.



Any frequency from 1 MHz to 60 MHz in 1 Hz steps

Factory programmable options for short lead times

Best dynamic stability under airflow, thermal shock



0.009 ppb/g or 0.1 ppb/g acceleration sensitivity



±0.5 ppm stability across temperature



±15 ppb/°C typical

frequency slope (ΔF/ΔT)

-40°C to +105°C operating temperature



Extended cold temperature option down to -55°C

No activity dips or micro jumps

Resistant to shock, vibration and board bending

On-chip regulators eliminate the need for external LDOs

Digital frequency pulling (DCTCXO) via I



Digital control of output frequency and pull range



Up to

±3200

ppm pull range



Frequency pull resolution down to 5 ppt

2.5 V, 2.8 V, 3.0 V and 3.3 V supply voltage

LVCMOS or clipped sinewave output

RoHS and REACH compliant

Pb-free, Halogen-free, Antimony-free

Applications



Ballistics, missiles, munitions

Military portable radios

Ruggedized communications networks

Precision GNSS systems

SATCOM

Transponders

Block Diagram

5.0 mm x 3.2 mm Package Pinout

SDA / NC

OE / VC / NC

SCL / NC

GND

VDD

CLK

A0 / NC

Figure 1. SiT5146 Block Diagram

Figure 2. Pin Assignments (Top view)

Refer to

Table 14

for Pin Descriptions

Rev 1.1

26 April 2021

www.sitime.com

SiT5146

1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Endura™ Series Super-TCXO

TABLE OF CONTENTS

Description ................................................................................................................................................................................... 1

Features....................................................................................................................................................................................... 1

Applications ................................................................................................................................................................................. 1

Block Diagram ............................................................................................................................................................................. 1

5.0 mm x 3.2 mm Package Pinout ............................................................................................................................................... 1

Ordering Information .................................................................................................................................................................... 2

Electrical Characteristics.............................................................................................................................................................. 4

Device Configurations and Pin-outs ............................................................................................................................................. 9

Pin-out Top Views................................................................................................................................................................. 9

Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ......................................................................................... 10

Waveforms................................................................................................................................................................................. 12

Timing Diagrams ........................................................................................................................................................................ 12

Typical Performance Plots ......................................................................................................................................................... 13

Architecture Overview ................................................................................................................................................................ 15

Frequency Stability ............................................................................................................................................................. 15

Output Frequency and Format............................................................................................................................................ 15

Output Frequency Tuning ................................................................................................................................................... 15

Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 16

Device Configurations ................................................................................................................................................................ 16

TCXO Configuration ........................................................................................................................................................... 16

VCTCXO Configuration ...................................................................................................................................................... 17

DCTCXO Configuration ...................................................................................................................................................... 18

VCTCXO-Specific Design Considerations ................................................................................................................................. 19

Linearity .............................................................................................................................................................................. 19

Control Voltage Bandwidth ................................................................................................................................................. 19

FV Characteristic Slope K

................................................................................................................................................. 19

Pull Range, Absolute Pull Range ........................................................................................................................................ 20

DCTCXO-Specific Design Considerations ................................................................................................................................. 21

Pull Range and Average Pull Range .................................................................................................................................. 21

Output Frequency ............................................................................................................................................................... 22

C Control Registers .......................................................................................................................................................... 24

Register Descriptions.......................................................................................................................................................... 24

Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 24

Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW)......................................... 25

Register Address: 0x02. DIGITAL PULL RANGE CONTROL ............................................................................................ 26

Serial Interface Configuration Description .......................................................................................................................... 27

Serial Signal Format ........................................................................................................................................................... 27

Parallel Signal Format ........................................................................................................................................................ 28

Parallel Data Format ........................................................................................................................................................... 28

C Timing Specification ...................................................................................................................................................... 30

C Device Address Modes ................................................................................................................................................. 31

Schematic Example ............................................................................................................................................................ 32

Dimensions and Patterns ........................................................................................................................................................... 33

Layout Guidelines ...................................................................................................................................................................... 34

Manufacturing Guidelines .......................................................................................................................................................... 34

Additional Information ................................................................................................................................................................ 35

Revision History ......................................................................................................................................................................... 36

Rev 1.1

Page 3 of 36

www.sitime.com

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