Integrated
Circuit
Systems, Inc.
ICS853310
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
F
EATURES
•
Eight differential 3.3V LVPECL / ECL outputs
•
Two selectable differential LVPECL input pairs
•
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
•
Output frequency: >2GHz (typical)
•
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLKx input
•
Output skew: 50ps (maximum)
•
Part-to-part skew: 200ps (maximum)
•
Propagation delay: 900ps (maximum)
•
LVPECL mode operating voltage supply range:
V
CC
= 3V to 3.8V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3V to -3.8V
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS-compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS853310 is a low skew, high perfor-
mance 1-to-8 Differential-to-3.3V LVPECL/ECL
HiPerClockS™
Fa n o u t B u f fe r a n d a m e m b e r o f t h e
HiPerClockS ™ family of High Performance
Clock Solutions from ICS. The PCLKx, nPCLKx
pairs can accept LVPECL, LVDS, CML and SSTL differential
input levels. The ICS853310 is characterized to operate from
a 3.3V power supply. Guaranteed output and part-to-part
skew characteristics make the ICS853310 ideal for those
clock distribution applications demanding well defined per-
formance and repeatability.
IC
S
B
LOCK
D
IAGRAM
PCLK0
nPCLK0
PCLK1
nPCLK1
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
CLK_SEL
Q3
nQ3
Q4
nQ4
V
BB
Q5
nQ5
Q6
nQ6
Q7
nQ7
P
IN
A
SSIGNMENT
V
CCO
nQ0
nQ1
nQ2
Q0
Q1
Q2
V
EE
CLK_SEL
PCLK0
V
CC
nPCLK0
V
BB
PCLK1
25
26
27
28
1
2
3
4
5
nPCLK1
24
23
22
21
20 19
18
17
16
Q3
nQ3
Q4
V
CCO
nQ4
Q5
nQ5
ICS853310
15
14
13
12
11
Q6
6
nc
7
nQ7
8
V
CCO
9
Q7
10
nQ6
28-Lead PLCC
11.6mm x 11.4mm x 4.1mm package body
V Package
Top View
853310AV
www.icst.com/products/hiperclocks.html
1
REV. A
OCTOBER 27,
2008
Integrated
Circuit
Systems, Inc.
ICS853310
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
Type
Description
Core supply pin.
Pullup/
Inver ting differential LVPECL clock input. V
CC
/2.
Pulldown
Bias voltage.
Pulldown Non-inver ting differential LVPECL clock input.
Pullup/
Inver ting differential LVPECL clock input. V
CC
/2.
Pulldown
No connect.
Differential output pair. LVPECL interface levels.
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
Clock Select input. When HIGH, selects PCLK1, nPCLK1 inputs. When
Pulldown
LOW, selects PCLK0, nPCLK0 inputs. LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential LVPECL clock input.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7, 9
8, 15, 22
10, 11
12, 13
14, 16
17, 18
19, 20
21, 23
24, 25
26
27
28
Name
V
CC
nPCLK0
V
BB
PCLK1
nPCLK1
nc
nQ7, Q7
V
CCO
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
V
EE
CLK_SEL
PCLK0
Power
Input
Output
Input
Input
Unused
Output
Power
Output
Output
Output
Output
Output
Output
Output
Power
Input
Input
853310AV
www.icst.com/products/hiperclocks.html
2
REV. A OCTOBER 27, 2008
Integrated
Circuit
Systems, Inc.
ICS853310
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
4.6V (LVPECL mode, V
EE
= 0)
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
-4.6V (LVECL mode, V
CC
= 0)
to the device. These ratings are stress specifi-
-0.5V to V + 0.5 V
CC
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(LVECL mode)
Outputs, I
O
Continuous Current
Surge Current
V
BB
Sink/Source, I
BB
Storage Temperature, T
STG
Wave Solder, T
SOL
0.5V to V
EE
- 0.5V
50mA
100mA
± 0.5mA
-65°C to 150°C
265°C
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Operating Temperature Range, TA -40°C to +85°C
T
ABLE
2A. LVPECL P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3V
TO
3.8V; V
EE
= 0V
Symbol
V
CC
V
CCO
I
EE
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.0
3.0
Typical
3.3
3. 3
Maximum
3.8
3.8
70
Units
V
V
mA
Table 2B. LVPECL DC Characteristics,
V
CC
= 3.3V; V
EE
= 0V
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage
(Single-Ended
)
Input Low Voltage
(Single-Ended)
Output Voltage Reference; NOTE 2
-40°C
Min
2.175
1.405
2.075
1.43
1.86
Typ
2.275
1.545
Max
2.38
1.68
2.36
1.765
1.98
Min
2.225
1.425
2.075
1.43
1.86
25°C
Typ
2.295
1.52
Max
2.37
1.615
2.36
1.765
1.98
Min
2.295
1.44
2.075
1.43
1.86
1.765
1.98
85°C
Typ
2.22
1.535
Ma x
2.365
1.63
Unit-
s
V
V
V
V
mV
Peak-to-Peak Input Voltage
500
1000
500
1000
500
1000
mV
Input High Voltage
V
CMR
1.8
2.9
1. 8
2. 9
1.8
2.9
V
Common Mode Range; NOTE 3
PCLK0, PCLK1
Input High
I
IH
150
150
150
µA
nPCLK0, nPCLK1
Current
CLK_SEL
PCLK0, PCLK1,
Input Low
nPCLK0, nPCLK1
I
IL
-150
-150
-150
µA
Current
CLK_SEL
NOTE 1: Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3V.
Please refer to Parameter Measurement Information, "Output Load AC Test Circuit".
NOTE 2: Outputs terminated with 50
Ω
to V
CCO
- 2V.
NOTE 3: V
CMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. V
CMR
is defined as the range within which the V
IH
level may
vary, with the device still meeting the propagation delay specification. The V
IL
level must be such that the peak-to-peak
voltage is less than 1V and greater than or equal to V
PP
(min).
853310AV
www.icst.com/products/hiperclocks.html
3
REV. A OCTOBER 27, 2008
Integrated
Circuit
Systems, Inc.
ICS853310
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
Test Conditions
Minimum
-3.0
Typical
-3.3
Maximum
-3.8
70
Units
V
mA
T
ABLE
2C. LVECL P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3.3V ± 0.3V
Symbol
V
EE
I
EE
Parameter
Supply Voltage
Power Supply Current
Table 2D. ECL DC Characteristics,
V
CC
= 0V; V
EE
= -3.3V ± 0.3V
Symbol
V
OH
V
OL
V
IH
V
IL
Parameter
Output High Voltage
Output Low Voltage
Input High Voltage
(Single-Ended)
-40°C
Min
-1.125
-1.895
-1.225
Typ
-1.025
-1.755
Max
-0.92
-1.62
-0.94
Min
-1.075
-1.875
-1.225
25°C
Typ
-1.005
-1.78
Max
-0.93
-1.685
-0.94
Min
-1.005
-1.86
-1.225
85°C
Typ
-1.08
-1.765
Max
-0.935
-1.67
Units
V
V
V
Input Low Voltage
(Single-Ended)
-1.87
-1.535 -1.87
-1.535 -1.87
-1.535
V
Output Voltage Reference;
-1.44
-1.32
-1.44
-1.32
-1.44
-1.32
mV
V
BB
NOTE 1
Peak-to-Peak Input Voltage
500
1000
500
1000
500
1000
mV
V
PP
Input High Voltage
1.5
-0.4
1.5
-0.4
1.5
-0.4
V
V
CMR
Common Mode Range; NOTE 2
PCLK0, PCLK1,
Input High
I
IH
nPCLK0, nPCLK1
150
150
150
µA
Current
CLK_SEL
PCLK0, PCLK1,
Input Low
IIL
nPCLK0, nPCLK1
-150
-150
-150
µA
Current
CLK_SEL
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
NOTE 2: V
CMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. V
CMR
is defined as the range within which the V
IH
level may
vary, with the device still meeting the propagation delay specification. The V
IL
level must be such that the peak-to-peak
voltage is less than 1V and greater than or equal to V
PP
(min).
T
ABLE
3. AC C
HARACTERISTICS
,
V
CC
= 3.3V; V
EE
= 0V
OR
V
CC
= 0V; V
EE
= -3.3V
Symbol
f
MAX
t
PD
t
sk(o)
t
sk(pp)
t
R
/t
F
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
20% to 80%
10 0
700
-40°C
Min
Typ
>2
90 0
75
250
400
100
750
Max
Min
25°C
Typ
>2
950
50
200
400
100
775
Max
Min
85°C
Typ
>2
975
50
200
400
Max
Units
GHz
ps
ps
ps
ps
V
EE
can ver y ± 0.3V.
All parameters measured at ƒ
≤
1.2GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853310AV
www.icst.com/products/hiperclocks.html
4
REV. A OCTOBER 27, 2008
Integrated
Circuit
Systems, Inc.
ICS853310
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
2V
V
CC
Qx
SCOPE
V
CC
LVPECL
nQx
V
EE
nPCLK0,
nPCLK1
V
PCLK0,
PCLK1
PP
Cross Points
V
CMR
-1.3V ± 0.3V
V
EE
O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
nQx
Qx
nQx
PART 1
Qx
nQy
nQy
Qy
PART 2
Qy
tsk(pp)
tsk(o)
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
nPCLK0,
nPCLK1
PCLK0,
PCLK1
nQ0:nQ7
Q0:Q7
t
PD
80%
Clock
Outputs
80%
V
SW I N G
20%
t
R
t
F
20%
P
ROPAGATION
D
ELAY
853310AV
O
UTPUT
R
ISE
/F
ALL
T
IME
www.icst.com/products/hiperclocks.html
5
REV. A OCTOBER 27, 2008
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