PRELIMINARY
ICS858012
L
OW
S
KEW
, 1-
TO
-2, D
IFFERENTIAL
-
TO
-
2.5V, 3.3V LVPECL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS858012 is a high speed 1-to-2 Differential-
to-2.5V, 3.3V LVPECL Fanout Buffer and is a
HiPerClockS™
member of the HiPerClockS™ family of high
performance clock solutions from ICS. The
ICS858012 is optimized for high speed and very
low output skew, making it suitable for use in demanding
applications such as SONET, 1 Gigabit and 10 Gigabit
Ethernet, and Fibre Channel. The internally terminated
differential input and V
REF
_
AC
pin allow other differential signal
families such as LVPECL, LVDS, LVHSTL and HCSL to be
easily interfaced to the input with minimal use of external
components. The ICS858012 is packaged in a small 3mm x
3mm 16-pin VFQFN package which makes it ideal for use in
space-constrained applications.
F
EATURES
•
Two differential LVPECL outputs
•
One differential LVPECL clock input
•
IN, nIN pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Output frequency: 2GHz (typical)
•
Output skew: <15ps (typical)
•
Part-to-part skew: TBD
•
Additive phase jitter, RMS: TBD
•
Propagation delay: 350ps (typical)
•
Operating voltage supply range:
V
CC
= 2.375V to 3.63V, V
EE
= 0V
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS5) and lead-free (RoHS 6)
packages
ICS
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
V
CC
IN 1
V
T
2
Q0
nQ0
V
REF
_
AC
3
nIN 4
16 15 14 13
12
11
10
9
5
V
CC
V
CC
V
EE
V
EE
Q0
nQ0
nQ1
Q1
V
EE
V
EE
Q1
nQ1
V
REF_AC
ICS858012
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product
characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifica-
tions without notice.
858012AK
V
CC
IN
V
T
nIN
6
7
8
1
REV. A OCTOBER 28, 2008
PRELIMINARY
ICS858012
L
OW
S
KEW
, 1-
TO
-2, D
IFFERENTIAL
-
TO
-
2.5V, 3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5, 8, 13, 16
6, 7, 14, 15
9, 10
11, 12
Name
IN
V
T
V
REF_AC
nIN
V
CC
V
EE
Q1, nQ1
nQ0, Q0
Input
Input
Output
Input
Power
Power
Output
Output
Type
Description
Non-inver ting LVPECL differential clock input.
Termination input.
Reference voltage for AC-coupled applications.
V
REF_AC
= to V
CC
- 1.38V.
Inver ting differential LVPECL clock input.
Positive supply pins.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
858012AK
2
REV. A OCTOBER 28, 2008
PRELIMINARY
ICS858012
L
OW
S
KEW
, 1-
TO
-2, D
IFFERENTIAL
-
TO
-
2.5V, 3.3V LVPECL F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Input Current, IN, nIN
V
T
Current, I
VT
Input Sink/Source, I
REF_AC
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
4.6V (LVPECL mode, V
EE
= 0)
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
-0.5V to V
CC
+ 0.5 V
to the device. These ratings are stress specifi-
50mA
cations only. Functional operation of product at
100mA
these conditions or any conditions beyond those
±50mA
listed in the
DC Characteristics
or
AC Character-
±100mA
± 0.5mA
-65°C to 150°C
51.5°C/W (0 lfpm)
Operating Temperature Range, TA -40°C to +85°C
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
T
ABLE
2A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375V
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
TO
3.63V; V
EE
= 0V
Minimum
2.375
Typical
3.3
30
Maximum
3.63
Units
V
mA
Test Conditions
Max., V
CC
, No Load
T
ABLE
2B. DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.63V; V
EE
= 0V
Symbol
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
I
N
to V
T
V
REF_AC
Output Reference Voltage
V
CC
- 1.525
V
CC
- 1.4
NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing Diagram
Parameter
Differential Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing; NOTE 1
Differential Input Voltage Swing
(IN, nIN)
(IN, nIN)
(IN, nIN)
Test Conditions
Minimum
40
1.2
0
0.1
0.3
1.28
V
CC
- 1.325
Typical
50
Maximum
60
V
CC
V
IH
- 0.15
1.7
Units
Ω
V
V
V
V
V
V
T
ABLE
2C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.63V; V
EE
= 0V
Symbol
V
OH
V
OL
V
OUT
V
DIFF_OUT
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Voltage Swing
Differential Output Voltage Swing
Conditions
Minimum
V
CC
- 1.145
V
CC
- 1.945
550
1100
800
1600
Typical
Maximum
V
CC
- 0.895
V
CC
- 1.695
Units
V
V
mV
mV
NOTE 1: Outputs terminated with 100
Ω
across differential output pair.
858012AK
3
REV. A OCTOBER 28, 2008
PRELIMINARY
ICS858012
L
OW
S
KEW
, 1-
TO
-2, D
IFFERENTIAL
-
TO
-
2.5V, 3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
3. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3.63V
TO
-2.375V
OR
V
CC
= 2.375
TO
3.63V; V
EE
= 0V
Symbol
f
MAX
f
IN
Parameter
Output Frequency
Input Frequency
Propagation Delay; (Differential);
NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Output Rise/Fall Time
20% to 80%
Condition
Minimum
Typical
2
2.5
350
<15
TBD
TBD
152
Maximum
Units
GHz
GHz
ps
ps
ps
fs
ps
t
PD
t
sk(o)
t
sk(pp)
t
jit
t
R
/t
F
All parameters characterized at
≤
1GHz unless otherwise noted.
R
L
= 100
Ω
after each output pair.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
858012AK
4
REV. A OCTOBER 28, 2008
PRELIMINARY
ICS858012
L
OW
S
KEW
, 1-
TO
-2, D
IFFERENTIAL
-
TO
-
2.5V, 3.3V LVPECL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
2V
V
CC
V
CC
Qx
SCOPE
nIN
LVPECL
V
EE
nQx
IN
V
IN
Cross Points
V
IH
V
IL
V
EE
-0.375V to -1.63V
O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
nQx
PART 1
Qx
nQy
PART 2
Qy
tsk(pp)
nQx
Qx
nQy
Qy
tsk(o)
P
ART
-
TO
-P
ART
S
KEW
nIN
IN
nQ0, nQ1
Q0, Q1
t
PD
O
UTPUT
S
KEW
V
IN
V
IN
, V
OUT
800mV
(typical)
V
DIF_IN
V
DIFF_IN
, V
DIFF_OUT
1.6V
(typical)
P
ROPAGATION
D
ELAY
S
INGLE
E
NDED
& D
IFFERENTIAL
I
NPUT
V
OLTAGE
S
WING
80%
Clock
Outputs
80%
V
SW I N G
20%
t
R
t
F
20%
O
UTPUT
R
ISE
/F
ALL
T
IME
858012AK
5
REV. A OCTOBER 28, 2008
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