IC,LOGIC GATE,DUAL 4-INPUT NAND,CMOS,DIP,14PIN,CERAMIC
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | NXP |
| package instruction | DIP, DIP14,.3 |
| Reach Compliance Code | unknown |
| series | 4000/14000/40000 |
| JESD-30 code | R-XDIP-T14 |
| JESD-609 code | e0 |
| length | 19.495 mm |
| Load capacitance (CL) | 50 pF |
| Logic integrated circuit type | NAND GATE |
| Number of functions | 2 |
| Number of entries | 4 |
| Number of terminals | 14 |
| Maximum operating temperature | 125 °C |
| Minimum operating temperature | -55 °C |
| Package body material | CERAMIC |
| encapsulated code | DIP |
| Encapsulate equivalent code | DIP14,.3 |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
| power supply | 5/15 V |
| propagation delay (tpd) | 300 ns |
| Certification status | Not Qualified |
| Schmitt trigger | NO |
| Maximum seat height | 5.08 mm |
| Maximum supply voltage (Vsup) | 18 V |
| Minimum supply voltage (Vsup) | 3 V |
| Nominal supply voltage (Vsup) | 5 V |
| surface mount | NO |
| technology | CMOS |
| Temperature level | MILITARY |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | THROUGH-HOLE |
| Terminal pitch | 2.54 mm |
| Terminal location | DUAL |
| Maximum time at peak reflow temperature | NOT SPECIFIED |
| width | 7.62 mm |
| Base Number Matches | 1 |
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