DATASHEET
BUFFER/CLOCK DRIVER
Description
The MK3805 is a non-inverting clock driver/buffer providing
two independent banks of four outputs each. These buffers
have a tri-state output enable input (active low) with 1-input,
5-output configuration per group. The skew between the
outputs of the same package is 0.5 ns and the skew
between the outputs of different packages is 0.8 ns. The
maximum input to output delay is 4.5 ns.
MK3805
Features
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Packaged in 20-pin SSOP
Available in Pb (lead) free package
Five outputs for each bank with one clock input
Two separate banks of five outputs each
Advanced, low-power, CMOS process
Ten output clocks
Two separate inputs
Industrial temperature range -40° C to +85° C
Hysteresis on all inputs
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Block Diagram
VDD
2
OEA
INA
OA0-4
5
OEB
INB
OB0-4
5
MON
3
GND
IDT™ / ICS™
BUFFER/CLOCK DRIVER
1
MK3805
REV D 122109
MK3805
BUFFER/CLOCK DRIVER
FAN OUT BUFFER
External Components
The MK3805 requires a minimum number of external
components for proper operation.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitors should be mounted on
the component side of the board as close to the VDD pins
as possible. No vias should be used between the
decoupling capacitors and VDD pins. The PCB trace to VDD
pin should be kept as short as possible, as should the PCB
trace to the ground via.
2) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through the signal
layers. Other signal traces should be routed away from the
MK3805. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
Decoupling Capacitors
Decoupling capacitors of 0.01µF must be connected
between VDD and GND, as close to these pins as possible.
For optimum device performance, the decoupling capacitors
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ω resistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω
.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK3805. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
-40 to +85° C
-65 to +150° C
125° C
260° C
IDT™ / ICS™
BUFFER/CLOCK DRIVER
3
MK3805
REV D 122109
京公网安备 11010802033920号
EEWORLD
