Short Form Data Sheet
August 2014
5- or 10-Output Any-to-Any Timing ICs
with Internal EEPROM
General Description
The MAX24305 and MAX24310 are flexible, high-
performance timing and clock synthesizer ICs that
include a DPLL and two independent APLLs. When
locked to one of two input clock signals, the device
performs any-to-any frequency conversion. From any
input clock frequency 1Hz to 750MHz the device can
produce frequency-locked APLL output frequencies up
to 750MHz and as many as 10 output clock signals that
are integer divisors of the APLL frequencies. Input jitter
can be attenuated by an internal low-bandwidth DPLL.
The DPLL also provides truly hitless switching between
input clocks and a high-resolution holdover capability.
Input switching can be manual or automatic. Using only
a low-cost crystal or oscillator, the device can also serve
as a frequency synthesizer IC. Output jitter is typically
0.18 to 0.3ps RMS for an APLL-only integer multiply
and 0.25 to 0.4ps RMS for
APLL-only fractional multiply
or DPLL+APLL operation
.
For telecom systems, the device has all required
features and functions to serve as a central timing
function or as a line card timing IC. With a suitable
oscillator the device meets the requirements of Stratum
2, 3E, 3, 4E, and 4; G.812 Types I to IV; G.813; and
G.8262.
MAX24305, MAX24310
Features
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Input Clocks
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One Crystal Input
Two Differential or CMOS/TTL Inputs
Differential to 750MHz, CMOS/TTL to 160MHz
Continuous Input Clock Quality Monitoring
Automatic or Manual Clock Selection
Hitless Reference Switching on Loss of Input
Programmable Bandwidth, 0.5mHz to 400Hz
Attenuates Jitter up to Several UI
Free-Run or Holdover on Loss of All Inputs
Hitless Reference Switching on Loss of Input
Manual Phase Adjustment
APLLs Perform High Resolution Fractional-N
Clock Multiplication
Any Output Frequency from <1Hz to 750MHz
Each Output Has an Independent Divider
Output Jitter Typically 0.18 to 0.3ps RMS for
APLL-Only Integer Multiply and 0.25 to 0.4ps
RMS for Other Modes (12kHz to 20MHz)
Outputs are CML or 2xCMOS, Can Interface to
LVDS, LVPECL, HSTL, SSTL and HCSL
CMOS Output Voltage from 1.5V to 3.3V
Suitable Line Card IC or Timing Card IC for
Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU
Automatic Self-Configuration at Power-Up
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Low-Bandwidth DPLL
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Two APLLs Plus 5 or 10 Output Clocks
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Frequency Conversion and Synthesis Applications in a
Wide Variety of Equipment Types
Telecom Timing Cards or Line Cards for SONET/SDH,
Synchronous Ethernet and/or OTN
Applications
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General Features
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Ordering Information
PART
MAX24305EXG+
MAX24310EXG+
OUTPUTS
5
10
TEMP
RANGE
-40 to +85
-40 to +85
PIN-
PACKAGE
81-CSBGA
81-CSBGA
from Internal EEPROM Memory
+Denotes
a lead(Pb)-free/RoHS-compliant package.
Uses External Crystal, Oscillator or Clock
Signal As Master Clock
Internal Compensation for Local Oscillator
Frequency Error
SPI Processor Interface
1.8V + 3.3V Operation (5V Tolerant)
-40
°C
to +85
°C
Operating Temp. Range
10mm x 10mm CSBGA Package
1
Short Form Data Sheet
MAX24305, MAX24310
1. Application Examples
Figure 1-1. Telecom Timing Card
Primary and secondary
clocks from clock
selector FPGA
19.44M,
25M, etc.
IC1P/N
IC2P/N
local
osc
MCP/N
OC1P/N
OC2P/N
OC3P/N
OC4P/N
OC5P/N
OC6P/N
OC7P/N
OC8P/N
OC9P/N
OC10P/N
System clocks to line cards
19.44M, 25M, etc.
Figure 1-2. Synchronous Ethernet and SDH/SONET Line Card
Synchronous Ethernet
Clocks: any combination
of 25M, 125M, 156.25M
and related frequencies
Any combination of differential or
2x single-ended signal format
From dual
redundant
timing functions
19.44M,
25M, etc.
IC1P/N
IC2P/N
OC1P/N
OC2P/N
OC3P/N
OC4P/N
OC5P/N
OC6P/N
OC7P/N
OC8P/N
OC9P/N
OC10P/N
local
osc
MCP/N
SDH/SONET Clocks:
Nx6.48MHz to 622.08MHz
2. Block Diagram
Figure 2-1. Block Diagram
Input Block
Scaler, Divider,
Monitor
DPLL
Hitless Switching,
Jitter Filtering,
Holdover
Figure 5-8
APLL1
3.7-4.2GHz,
Sub-ps jitter,
Fractional-N
A
B
DIV1
DIV2
DIV3
DIV4
DIV5
DIV6
DIV7
DIV8
DIV9
DIV10
OC1POS/NEG
OC2POS/NEG
OC3POS/NEG
OC4POS/NEG
OC5POS/NEG
OC6POS/NEG
OC7POS/NEG
OC8POS/NEG
OC9POS/NEG
OC10POS/NEG
Figure 5-7
Figure 5-10
C
MAX24310 only
IC1POS/NEG
IC2POS/NEG
MCLKOSCP/N
XIN
XOUT
APLL2
XO
and HW Control and Status Pins
3.7-4.2GHz,
Sub-ps jitter,
Fractional-N
D
MAX24310 only
SPI Interface
JTAG
GPIO1
AC / GPIO3
SS / GPIO4
GPIO2
TEST
RST_N
CS_N
SDI
JTRST_N
JTMS
JTCLK
JTDI
JTDO
INTREQ
SCLK
SDO
2
Short Form Data Sheet
MAX24305, MAX24310
3. Detailed Features
3.1
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•
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Two input clocks, differential or CMOS/TTL signal format
Input clocks can be any frequency from 1Hz up to 750MHz
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTU-1, OTU-2, OTU-3
Per-input fractional scaling (i.e. multiplying by N÷D where N is a 16-bit integer and D is a 32-bit integer and
N<D) to undo 64B/66B and FEC scaling (e.g. 64/66, 238/255, 237/255, 236/255)
All inputs constantly monitored by programmable activity monitors and frequency monitors
Fast activity monitor can disqualify the selected reference after a few missing clock cycles
Frequency measurement with 1.25ppm resolution
Frequency monitor thresholds with 1.25ppm or 5ppb resolution
Very high-resolution DPLL architecture
Sophisticated state machine automatically transitions between free-run, locked, and holdover states
Revertive or nonrevertive reference selection algorithm
Programmable bandwidth from 0.5mHz to 400Hz
Separately configurable acquisition bandwidth and locked bandwidth
Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10 or 20
Multiple phase detectors: phase/frequency and multicycle
Phase/frequency locking (±360° capture) or nearest-edge phase locking (±180° capture)
Multicycle phase detection and locking (up to
±8191UI)
improves jitter tolerance and lock time
Phase build-out in response to reference switching for true hitless switching
Less than 1 ns output clock phase transient during phase build-out
Output phase adjustment up to
±200ns
in 6ps steps with respect to selected input reference
High-resolution frequency and phase measurement
Holdover frequency averaging over 1 second, 5.8 minute and 93.2 minute intervals
Fast detection of input clock failure and transition to holdover mode
Two independent APLLs simultaneously product two frequency families from the same reference clock or
different reference clocks
Very high-resolution fractional scaling (i.e. non-integer multiplication)
Output jitter is typically
0.18 to 0.3ps RMS for APLL-only integer multiply and 0.25 to 0.4ps RMS for APLL-only
Telecom output frequencies include 622.08MHz for SONET/SDH and 625MHz for Synchronous Ethernet
Bypass mode for each APLL supports system testing and allows device to be used in fanout applications
Up to five (MAX24305) or ten (MAX24310) low-jitter output clocks
Each output can be one differential output or two CMOS/TTL outputs
Outputs easily interface with CML, LVDS, LVPECL, HSTL, SSTL, HCSL components
Each output can be any integer divisor of either APLL output clock
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN
Can also produce clock frequencies for microprocessors, ASICs, FPGAs and other components
Per-output delay adjustment
Per-output enable/disable
SPI serial microprocessor interface
fractional multiply or DPLL+APLL operation (12kHz to 20MHz integration band, for output frequencies >100MHz)
Input Block Features
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3.2
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DPLL Features
3.3
APLL Features
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3.4
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Output Clock Features
3.5
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General Features
Four general-purpose I/O pins
Can operate as DPLL+APLL for jitter filtering and hitless switching or as APLL only
Local oscillator can be nearly any frequency from 10MHz to 750MHz
Internal compensation for local oscillator frequency error
3
Automatic self-configuration at power-up from internal EEPROM memory
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.
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