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ZL30361GDG2

Description
IC network synch eth clk 144lbga
Categorysemiconductor    Analog mixed-signal IC   
File Size355KB,5 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Environmental Compliance  
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ZL30361GDG2 Overview

IC network synch eth clk 144lbga

ZL30361GDG2 Parametric

Parameter NameAttribute value
Datasheets
ZL30361
Standard Package160
CategoryIntegrated Circuits (ICs)
FamilyClock/Timing - Application Specific
PackagingTray
PLLYes
Main PurposeEthernet, Fibre Channel, SONET/SDH, Stratum
InpuClock
OutpuLVCMOS, LVPECL
Number of Circuits1
Ratio - InpuOutpu
Differential - InpuOutpu
Frequency - Max750MHz
Voltage - Supply*
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mou
Package / Case144-BGA
Supplier Device Package144-LBGA (13x13)
ZL30361
IEEE 1588 and Synchronous Ethernet Packet
Clock Network Synchronizer
Short Form Data Sheet
May 2013
Features
Frequency and Phase Sync over Packet Networks
Frequency accuracy performance for WCDMA-
FDD, GSM, LTE-FDD and femtocell applications
Frequency performance for ITU-T G.823 and
G.824 synchronization interface, as well as
G.8261 PNT PEC and CES interfaces
Phase Synchronization performance for
WCDMA-TDD, Mobile WiMAX, TD-SCDMA and
CDMA2000 applications
Client holdover and reference switching
between multiple Servers
Ordering Information
ZL30361GDG2 144 Pin LBGA
Pb Free Tin/Silver/Copper
-40
o
C to +85
o
C
Package size: 13 x 13 mm
Trays
Any input clock rate from 1 Hz to 750 MHz
Automatic hitless reference switching and digital
holdover on reference fail
Flexible two-stage architecture translates between
arbitrary data, line coding and FEC rates
Digital PLL with programmable bandwidth from
0.1 mHz up to 1 kHz
Programmable synthesizers
• Any output clock rate from 1Hz to 750MHz
Output jitter below 0.62 ps rms
Physical Layer Equipment Clocks Synchronizatin
ITU-T G.8262 for SyncE EEC option 1 and 2
ITU-T G.813 for SONET/SDH SEC option 1 and
2
Telcordia GR-1244 and GR-253 Stratum 3 and
SMC
Support for G.781 SETS
Operates from a single crystal resonator or clock
oscillator
Configurable via SPI/I
2
C interface
Osci
Osco
Ref0
Ref1
Ref2
Ref3
Ref4
Ref5
Ref6
Ref7
Ref8
Ref9
Ref10
Master Clock
Diff / Single Ended
Fr
0
= Br
0
*Kr
0
*Mr
0
/Nr
0
Diff / Single Ended
Fr
1
= Br
1
*Kr
1
*Mr
1
/Nr
1
Diff / Single Ended
Fr
2
= Br
2
*Kr
2
*Mr
2
/Nr
2
Diff / Single Ended
Fr
3
= Br
3
*Kr
3
*Mr
3
/Nr
3
Diff / Single Ended
Fr
4
= Br
4
*Kr
4
*Mr
4
/Nr
4
Diff / Single Ended
Fr
5
= Br
5
*Kr
5
*Mr
5
/Nr
5
Diff / Single Ended
Fr
6
= Br
6
*Kr
6
*Mr
6
/Nr
6
Diff / Single Ended
Fr
7
= Br
7
*Kr
7
*Mr
7
/Nr
7
Diff / Single Ended
Fr
8
= Br
8
*Kr
8
*Mr
8
/Nr
8
Single Ended
Fr
9
= Br
9
*Kr
9
*Mr
9
/Nr
9
Single Ended
Fr
10
= Br
10
*Kr
10
*Mr
10
/Nr
10
JTAG
Reference Monitors
State
Machine
ZL30361
Clock Generator 0
Synthesizer 0
Fs= Bs
0
*Ks
0
*16*Ms
0
/Ns
0
Div A
Div B
Div C
Div D
LVPECL
LVPECL
LVCMOS
LVCMOS
hpdiff0_p/n
hpdiff1_p/n
hpoutclk0
hpoutclk1
Clock Generator 1
DPLL/NCO
Select Loop band.,
Phase slope limit
Synthesizer 1
Fs= Bs
1
*Ks
1
*16*Ms
1
/Ns
1
Div A
Div B
Div C
Div D
LVPECL
LVPECL
LVCMOS
LVCMOS
hpdiff2_p/n
hpdiff3_p/n
hpoutclk2
hpoutclk3
Clock Generator 2
Synthesizer 2
Fs= Bs
2
*Ks
2
*16*Ms
2
/Ns
2
Div A
Div B
Div C
Div D
LVPECL
LVPECL
LVCMOS
LVCMOS
hpdiff4_p/n
hpdiff5_p/n
hpoutclk4
hpoutclk5
Configuration
and Status
JTAG
pwr_b
GPIO
SPI / I
2
C
Figure 1 - Functional Block Diagram
1
Copyright 2013, Microsemi Corporation. All Rights Reserved.
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