MAX24710EXG+ datasheet, PDF - EEWORLD Datasheet

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MAX24710EXG+: DescriptionSupport Circuit, 1-Func, PBGA81, 10 X 10 MM, ROHS COMPLIANT, CSBGA-81; CategoryThe embedded processor and controller Microcontrollers and processors; File Size282KB，4 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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MAX24710EXG+ Overview

Support Circuit, 1-Func, PBGA81, 10 X 10 MM, ROHS COMPLIANT, CSBGA-81

MAX24710EXG+ Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	1340172495
package instruction	LBGA, BGA81,9X9,40
Reach Compliance Code	compliant
ECCN code	EAR99
Samacsys Manufacturer	Microsemi Corporation
Samacsys Modified On	2019-04-07 09:50:24
JESD-30 code	S-PBGA-B81
length	10 mm
Number of terminals	81
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	750 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA81,9X9,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Master clock/crystal nominal frequency	50 MHz
Maximum seat height	1.47 mm
Maximum slew rate	575 mA
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	DUAL
width	10 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

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Short Form Data Sheet

August 2014

5- or 10-Output Any-to-Any Line Card Timing ICs

with Internal EEPROM

General Description

The MAX24705 and MAX24710 are flexible, high-

performance timing and clock synthesizer ICs that

include a DPLL and two independent APLLs. When

locked to one of two input clock signals, the device

performs any-to-any frequency conversion. From any

input clock frequency 1Hz to 750MHz the device can

produce frequency-locked APLL output frequencies up

to 750MHz and as many as 10 output clock signals that

are integer divisors of the APLL frequencies. Input jitter

can be attenuated by an internal low-bandwidth DPLL.

The DPLL also provides truly hitless switching between

input clocks and a high-resolution holdover capability.

Input switching can be manual or automatic. Using only

a low-cost crystal or oscillator, the device can also serve

as a frequency synthesizer IC. Output jitter is typically

0.18 to 0.3ps RMS for an APLL-only integer multiply

and 0.25 to 0.4ps RMS for

APLL-only fractional multiply

or DPLL+APLL operation

For telecom systems, the device has all required

features and functions to serve as a line card timing IC.

MAX24705, MAX24710

Features

♦

Input Clocks

♦

One Crystal Input

Two Differential or CMOS/TTL Inputs

Differential to 750MHz, CMOS/TTL to 160MHz

Continuous Input Clock Quality Monitoring

Automatic or Manual Clock Selection

Hitless Reference Switching on Loss of Input

Programmable Bandwidth, 4Hz to 400Hz

Attenuates Jitter up to Several UI

Free-Run or Holdover on Loss of All Inputs

Hitless Reference Switching on Loss of Input

Manual Phase Adjustment

APLLs Perform High Resolution Fractional-N

Clock Multiplication

Any Output Frequency from <1Hz to 750MHz

Each Output Has an Independent Divider

Output Jitter Typically 0.18 to 0.3ps RMS for

APLL-Only Integer Multiply and 0.25 to 0.4ps

RMS for Other Modes (12kHz to 20MHz)

Outputs are CML or 2xCMOS, Can Interface to

LVDS, LVPECL, HSTL, SSTL and HCSL

CMOS Output Voltage from 1.5V to 3.3V

Suitable Line Card IC for Stratum 2/3E/3/4E/4,

SMC, SEC/EEC, or SSU

Automatic Self-Configuration at Power-Up

♦

Low-Bandwidth DPLL

♦

Two APLLs Plus 5 or 10 Output Clocks

♦

Frequency Conversion and Synthesis Applications in a

Wide Variety of Equipment Types

Telecom Line Cards for SONET/SDH, Synchronous

Ethernet and Similar Applications

Applications

♦

Ordering Information

PART

MAX24705EXG+

MAX24710EXG+

OUTPUTS

TEMP

RANGE

-40 to +85

PIN-

PACKAGE

81-CSBGA

♦

General Features

♦

+Denotes

a lead(Pb)-free/RoHS-compliant package.

from Internal EEPROM Memory

Uses External Crystal, Oscillator or Clock

Signal As Master Clock

Internal Compensation for Local Oscillator

Frequency Error

SPI Processor Interface

1.8V + 3.3V Operation (5V Tolerant)

-40

°C

to +85

°C

Operating Temp. Range

10mm x 10mm CSBGA Package

MAX24710EXG+ Related Products

	MAX24710EXG+	MAX24705EXG+
Description	Support Circuit, 1-Func, PBGA81, 10 X 10 MM, ROHS COMPLIANT, CSBGA-81	IC clk synthesizer 5out 81csbga
Is it Rohs certified?	conform to	conform to
package instruction	LBGA, BGA81,9X9,40	LBGA, BGA81,9X9,40
Reach Compliance Code	compliant	compli
JESD-30 code	S-PBGA-B81	S-PBGA-B81
length	10 mm	10 mm
Number of terminals	81	81
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Maximum output clock frequency	750 MHz	750 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA
Encapsulate equivalent code	BGA81,9X9,40	BGA81,9X9,40
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Master clock/crystal nominal frequency	50 MHz	50 MHz
Maximum seat height	1.47 mm	1.47 mm
Maximum slew rate	575 mA	575 mA
Maximum supply voltage	1.89 V	1.89 V
Minimum supply voltage	1.71 V	1.71 V
Nominal supply voltage	1.8 V	1.8 V
surface mount	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	BALL
Terminal pitch	1 mm	1 mm
Terminal location	DUAL	DUAL
width	10 mm	10 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC	CLOCK GENERATOR, PROCESSOR SPECIFIC

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