PI6C182
PI6C182A
Precision 1-to-10 Clock Buffer
Features
• Low noise non-inverting 1-to-10 buffer
• Supports frequency up to 125 MHz (PI6C182A)
• Supports up to four SDRAM DIMMs
• Low skew (<200ps) between any two output clocks
• I
2
C Serial Configuration interface
• Multiple V
DD
and V
SS
pins for noise reduction
• 3.3V power supply voltage
• Separate Hi-Z state pin for testing
• Packaging (Pb-free & Green available):
— 28-pin SSOP (H)
Description
The PI6C182 is a high-speed low-noise 1-to-10 noninverting buf-
fer designed for SDRAM clock buffer applications, supporting
frequencies up to 110 MHz.
At power up all SDRAM output are enabled and active. The I
2
C
serial control may be used to individually activate/deactivate any
driver.
The output enable pin (OE) may be pulled LOW to tri-state all
outputs.
Note:
Purchases of I
2
C components from Pericom conveys a license of
use in I
2
C system defined by Philips Semiconductor.
Diagram
SDRAM0
Pin Configuration
VDD0
SDRAM1
BUF_IN
SDRAM2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD5
SDRAM7
SDRAM6
VSS5
VDD4
SDRAM5
SDRAM4
VSS4
OE
VDD3
SDRAM9
VSS3
VSSIIC
SCLOCK
SDRAM0
SDRAM1
VSS0
VDD1
SDRAM2
SDRAM3
SDRAM3
VSS1
BUF_IN
SDRAM9
OE
VDD2
SDRAM8
VSS2
SDATA
SCLOCK
I2C
I/O
VDDIIC
SDATA
08-0298
1
PS8165G
11/13/08
PI6C182, PI6C182A
Precision 1-to-10 Clock Buffer
Pin Description
Pin
2, 3, 6, 7
22, 23, 26, 27
11, 18
9
20
14
15
1, 5, 10, 19, 24,
28
4, 8, 12, 17, 21,
25
13
16
Symbol
SDRAM[0-3]
SDRAM[4-7]
SDRAM[8-9]
BUF_IN
OE
SDATA
SCLOCK
VDD[0-5]
VSS[0-5]
VDDIIC
VSSIIC
Type
O
O
O
I
I
I/O
I/O
Power
Ground
Power
Ground
Qty
4
4
2
1
1
1
1
6
6
1
1
SDRAM Byte 0 clock output
SDRAM Byte 1 clock output
SDRAM Byte 2 clock output
Input for 1-20 buffer
Hi-Z when LOW. Internal 100kΩ pull-up resistor.
Data pin for I
2
C curcuitry. Internal 100kΩ pull-up resistor.
Clock pin I
2
C circuitry. Internal 100kΩ pull-up resistor.
3.3V power supply for SDRAM buffers
Ground for SDRAM buffers
3.3V power supply for I
2
C circuitry
Ground for I
2
C circuitry
Description
OE Functionality
(1,2)
OE
0
1
SDRAM[0-9]
Hi-Z
BUF_IN
Serial Configuration Map
(1)
Byte0: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
7
6
5
4
3
A2
0
A1
0
A0
1
R/W
0
2
1
0
7
6
3
2
Pin
Description
NC (Initialize to 0)
NC (Initialize to 0)
NC (Initialize to 0)
NC (Initialize to 0)
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
SDRAM0 (Active/Inactive)
Notes:
1. Used for test purposes only
2. Buffers are non-inverting
I
2
C Address Assignment
A6
1
A5
1
A4
0
A3
1
Note:
1. Inactive means outputs are held LOW and are disabled from
switching
08-0298
2
PS8165G
11/13/08
PI6C182, PI6C182A
Precision 1-to-10 Clock Buffer
2-Wire I
2
C Control
The I
2
C interface permits individual enable/disable of each clock
output and test mode enable.
The PI6C182 is a slave receiver device. It can not be read back.
Sub-addressing is not supported. All preceding bytes must be sent
in order to change one of the control bytes.
Each byte on the SDATA line must be 8-bits long (MSB
fi
rst), fol-
lowed by an acknowledge bit generated by the receiver.
During normal data transfers SDATA changes only when SCLOCK
is LOW. Exceptions: A HIGH to LOW transition on SDATA while
SCLOCK is HIGH indicates a “start” condition. A LOW to HIGH
transition on SDATA while SCLOCK is HIGH indicates a “stop”
condition and indicates the end of a data transfer cycle.
Each data transfer is initiated with a start condition and ends with
a stop condition. The
fi
rst byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addressed device, LOW = write to addressed device). If the device’s
own address is detected, PI6C182 generates an acknowledge by
pulling SDATA line LOW during ninth clock pulse, then accepts
the following data bytes until another start or stop condition is
detected.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. “Command Code” byte
2. “Byte Count” byte.
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
Byte1: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
7
6
5
4
3
2
1
0
Pin
27
26
23
22
Description
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
NC (Initialize to 0)
NC (Initialize to 0)
NC (Initialize to 0)
NC (Initialize to 0)
Byte2: Optional Register for Possible Future
Requirements (1 = enable, 0 = disable)
Bit
7
6
5
4
3
2
1
0
Pin
18
11
Description
SDRAM9 (Active/Inactive)
SDRAM8 (Active/Inactive)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Maximum Ratings
Storage Temperature............................................................–65°C to +150°C
Ambient Temperature with Power Applied .............................–0°C to +70°C
3.3V Supply Voltage to Ground Potential ..............................–0.5V to +4.6V
DC Input Voltage ....................................................................–0.5V to +4.6V
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this speci
fi
cation is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
Supply Current
(V
DD
= +3.465V, C
LOAD
= Max.)
Symbol
I
DD
I
DD
I
DD
I
DD
08-0298
Parameter
Test Condidtion
BUF_IN = 0 MHz
BUF_IN = 66.66 MHz
BUF_IN = 100.00 MHz
BUF_IN = 133.00 MHz
Min.
Typ.
Max.
2
180
240
360
Units
Supply Current
mA
3
PS8165G
11/13/08
PI6C182, PI6C182A
Precision 1-to-10 Clock Buffer
DC Operating Specifications
(V
DD
= +3.3V ±5%, T
A
= 0°C to 70°C)
Symbol
V
IH
V
IL
I
IL
V
OH
V
OL
C
OUT
C
IN
L
PIN
T
A
Parameter
Input High voltage
Input Low voltage
Input leakage current
Output High voltage
Output Low voltage
Output pin capacitance
Input pin capacitance
Pin Inductance
Ambient Temperature
No Airflow
0
0 < V
IN
< V
DD
I
OH
= -1mA
I
OL
= 1mA
6
5
7
70
nH
°C
Test Conditions
V
DD
Min.
2.0
V
SS
-0.3
-5
2.4
0.4
pF
Typ.
Max.
V
DD
+0.3
0.8
5
mA
V
Units
V
SDRAM Clock Buffer Operating Specification
Symbol
I
OHMIN
I
OHMAX
I
OLMIN
I
OLMAX
Parameter
Pull-up current
Pull-up current
Pull-down current
Pull-down current
Test Conditions
V
OUT
= 2.0V
V
OUT
= 3.135V
V
OUT
= 1.0V
V
OUT
= 0.4V
40
38
Min.
-40
-36
mA
Typ.
Max.
Units
AC Timing
Symbol
t
SDRISE
t
SDFALL
t
PLH
t
PHL
t
PZL
, t
PZH
t
PLZ
, t
PHZ
Duty Cycle
t
SDSKW
Parameter
SDRAM CLK rise time
SDRAM CLK fall time
SDRAM Buffer LH prop delay
SDRAM Buffer HL prop delay
SDRAM Buffer Enable delay
(1)
SDRAM Buffer DIsable delay
(1)
Measured at 1.5V
SDRAM Output-to-Output skew
66 MHz
Min.
1.5
1.5
1.0
1.0
1.0
1.0
45
Max.
4.0
4.0
5.5
5.5
8.0
8.0
55
250
100 MHz
Min.
1.5
1.5
1.0
1.0
1.0
1.0
45
Max.
4.0
4.0
5.5
5.5
8.0
8.0
55
250
125MHz
Min.
1.5
1.5
1.0
1.0
1.0
1.0
45
Max.
4.0
4.0
5.5
5.5
8.0
8.0
55
200
%
ps
ns
Units
V/ns
Note:
1. This Parameter specified at 5MHz input frequency.
08-0298
4
PS8165G
11/13/08
PI6C182, PI6C182A
Precision 1-to-10 Clock Buffer
Output
Buffer
Test
Point
Test Load
tSDKP
tSDKH
3.3V
Clocking
Interface
(TTL)
2.4
1.5
0.4
tSDKL
tSDRISE
tSDFALL
Input
Waveform
tplh
Output
Waveform
1.5V
1.5V
tphl
1.5V
1.5V
Figure 1. Clock Waveforms
Minimum and Maximum Expected
(1,2,3)
Capacitive Loads
Clock
SDRAM
Min.
20
Max.
30
Units
pF
Notes
SDRAM DIMM
Specificaion
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to
the respective clock pins. Typical value for CI is 10pF. Series
resistor value can be increased to reduce EMI provided that
the rise and fall time are still within the specified values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over
a continuous power plane. Avoid routing clock traces from
plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables
or any external connectors.
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified
load.
2. Minimum rise/fall times are guaranteed at minimum specified
load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500Ω resistor in parallel.
08-0298
5
PS8165G
11/13/08
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