VCXO-To-6 LVCMOS Outputs
ICS81006I
DATA SHEET
General Description
The ICS81006I is a high performance, low jitter/ low phase noise
VCXO. The ICS81006I works in conjunction with a pullable crystal to
generate an output clock over the range of 12MHz – 31.25MHz and
has 6 LVCMOS outputs, effectively integrating a fanout buffer function.
The frequency of the VCXO is adjusted by the VC control voltage
input. The output range is ±100ppm around the nominal crystal
frequency. The VC control voltage range is 0 – V
DD
. The device is
packaged in a small 4mm x 4mm VFQFN package and is ideal for use
on space constrained boards typically encountered in ADSL/VDSL
applications.
Features
• Six LVCMOS/LVTTL outputs, 20 nominal output impedance
• Output Q5 can be selected for ÷1 or ÷2 frequency relative to the
crystal frequency
• Output frequency range: 12MHz to 31.25MHz
• Crystal pull range: ±90ppm (typical)
• Synchronous output enable places outputs in High-
Impedance state
• On-chip filter on VIN to suppress noise modulation of VCXO
• V
DD
/V
DDO
combinations
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• 4mm x 4mm 20-Lead VFQFN package is ideal for space
constrained designs
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Block Diagram
OE0
Pullup
Pin Assignment
GND
VC
LP Filter
Q0
XTAL_IN
XTAL_OUT
V
DD
1
2
3
4
5
20 19 18 17 16
15
14
13
12
6
OE1
Q0
Q1
SYNC
V
DDO
OE0
GND
Q2
V
DDO
Q3
GND
XTAL_IN
Q1
VC
DIV_SEL_Q5
VCXO
Q2
XTAL_OUT
Q3
7
GND
8
Q5
9
V
DDO
11
10
Q4
ICS81006I
20-Lead VFQFN
4mm x 4mm x 0.925 package body
K Package
Top View
Q4
0: ÷1
1: ÷2
DIV_SEL_Q5
Pulldown
Q5
OE1
Pullup
SYNC
ICS81006I REVISION B 07/25/14
1
©2014 Integrated Device Technology, Inc.
ICS81006I DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
1
Number
1, 2
3
4
5
6
7, 11, 15, 19
8, 10, 12, 14,
16, 18
9, 13, 17
20
Name
XTAL_IN,
XTAL_OUT
V
DD
VC
DIV_SEL_Q5
OE1
GND
Q5, Q4, Q3,
Q2, Q1, Q0
V
DDO
OE0
Input
Power
Input
Input
Input
Power
Output
Power
Input
Pullup
Pulldown
Pullup
Type
Description
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Positive supply pin.
Control voltage input.
Output divider select pin for Q5 output. When LOW, ÷1. When HIGH, ÷2.
LVCMOS/LVTTL interface levels.
Output enable pin. When HIGH, Q5 output is enabled. When LOW, forces
Q5 to a high impedance state. LVCMOS/LVTTL interface levels.
Power supply ground.
Single-ended clock outputs. LVCMOS/LVTTL interface levels. 20output
impedance.
Output supply pins.
Output enable pin. When HIGH, Q0:Q4 outputs are enabled. When LOW,
forces Q0:Q4 to a high impedance state. LVCMOS/LVTTL interface levels.
NOTE 1:
Pullup
and
Pulldown
refers to internal input resistors. See
Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
Parameter
Input
Capacitance
OE0, OE1
V
DD
= V
DDO
= 3.465V
C
PD
Power Dissipation
Capacitance
V
DD
= 3.465V or 2.625V,
V
DDO
= 2.625V
V
DD
= 3.465V or 2.625V,
V
DDO
= 2V
R
PULLUP
R
PULLDOWN
Input Pullup Resistor
Input Pulldown Resistor
V
DDO
= 3.3V
R
OUT
Output Impedance
V
DDO
= 2.5V
V
DDO
= 1.8V
51
51
20
25
38
Test Conditions
Minimum
Typical
4
3
4
Maximum
Units
pF
pF
pF
6
pF
k
k
VCXO-TO-6 LVCMOS OUTPUTS
2
REVISION B 07/25/14
ICS81006I DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Electrical Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
60.4°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= 3.3V±5%, V
DDO
= 3.3V ±5%, 2.5V ±5% or 1.8V ±0.2V, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Test Conditions
Minimum
3.135
3.135
Output Supply Voltage
2.375
1.6
Power Supply Current
Output Supply Current
Typical
3.3
3.3
2.5
1.8
Maximum
3.465
3.465
2.625
2.0
50
20
Units
V
V
V
V
mA
mA
Table 3B. Power Supply DC Characteristics,
V
DD
= 2.5V±5%, V
DDO
= 2.5V ±5% or 1.8V ±0.2V, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
1.6
Typical
2.5
2.5
1.8
Maximum
2.625
2.625
2.0
50
20
Units
V
V
V
mA
mA
REVISION B 07/25/14
3
VCXO-TO-6 LVCMOS OUTPUTS
ICS81006I DATA SHEET
Table 3C. LVCMOS/LVTTL DC Characteristics,
T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
VC
I
IH
I
IL
I
I
V
OH
Parameter
Input High Voltage
Input Low
Voltage
OE0, OE1,
DIV_SEL_Q5
Test Conditions
V
DD
= 3.3V ±5%
V
DD
= 2.5V ±5%
V
DD
= 3.3V ±5%
V
DD
= 2.5V ±5%
V
DD
= 3.3V or 2.5V ±5%
V
DD
= 3.3V or 2.5V ±5%
V
DD
= 3.3V or 2.5V ±5%
V
DD
= 3.3V or 2.5V ±5%
V
DD
= 3.465V or 2.625V
V
DDO
= 3.3V ±5%
Output High Voltage
1
V
DDO
= 2.5V ±5%
V
DDO
= 1.8V ±0.2V
V
OL
Output Low Voltage
1
V
DDO
= 3.3V or 2.5V ±5%
V
DDO
= 1.8V ±0.2V
-5
-150
-100
2.6
1.8
1.5
0.5
0.4
100
Minimum
2
1.7
-0.3
-0.3
0
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
V
DD
150
5
Units
V
V
V
V
V
µA
µA
µA
µA
µA
V
V
V
V
V
VCXO Control Voltage
Input
High Current
Input
Low Current
DIV_SEL_Q5
OE0, OE1
DIV_SEL_Q5
OE0, OE1
Input Current of VC pin
NOTE 1: Outputs terminated with 50to V
DDO
/2. See
Parameter Measurement Information
section, “Load Test Circuit” diagrams.
VCXO-TO-6 LVCMOS OUTPUTS
4
REVISION B 07/25/14
ICS81006I DATA SHEET
AC Characteristics
Table 4A. AC Characteristics,
V
DD
= V
DDO
= 3.3V ±5%, T
A
= -40°C to 85°C
Symbol
f
OUT
tjit(Ø)
tsk(o)
t
R
/ t
F
odc
Parameter
Output Frequency
RMS Phase Jitter (Random)
1
Output Skew
2, 3
Q0:Q4
Q0:Q5
DIV_SEL_Q5 = ÷1
20% to 80%
200
44
Integration Range: 1kHz – 1MHz
Test Conditions
Minimum
12
Typical
19.44
0.35
30
100
750
56
Maximum
31.25
Units
MHz
ps
ps
ps
ps
%
Output Rise/Fall Time
Output Duty Cycle
NOTE 1: Refer to the
Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
crosspoints.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Table 4B. AC Characteristics,
V
DD
= 3.3V ±5%, V
DDO
= 2.5V ±5%, T
A
= -40°C to 85°C
Symbol
f
OUT
tjit(Ø)
tsk(o)
t
R
/ t
F
odc
Parameter
Output Frequency
RMS Phase Jitter (Random)
1
Output Skew
2, 3
Q0:Q4
Q0:Q5
DIV_SEL_Q5 = ÷1
20% to 80%
300
45
Integration Range: 1kHz – 1MHz
Test Conditions
Minimum
12
Typical
19.44
0.38
20
90
800
55
Maximum
31.25
Units
MHz
ps
ps
ps
ps
%
Output Rise/Fall Time
Output Duty Cycle
NOTE 1: Refer to the
Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
crosspoints.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Table 4C. AC Characteristics,
V
DD
= 3.3V ±5%, V
DDO
= 1.8V ±0.2V, T
A
= -40°C to 85°C
Symbol
f
OUT
tjit(Ø)
tsk(o)
t
R
/ t
F
odc
Parameter
Output Frequency
RMS Phase Jitter (Random)
1
Output Skew
2, 3
Q0:Q4
Q0:Q5
DIV_SEL_Q5 = ÷1
20% to 80%
450
45
Integration Range: 1kHz – 1MHz
Test Conditions
Minimum
12
Typical
19.44
0.27
50
180
1400
55
Maximum
31.25
Units
MHz
ps
ps
ps
ps
%
Output Rise/Fall Time
Output Duty Cycle
NOTE 1: Refer to the
Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
crosspoints.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
REVISION B 07/25/14
5
VCXO-TO-6 LVCMOS OUTPUTS
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