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87339AMI-11LF

Description
IC clk gen 3.3V lvpecl 20-soic
Categorysemiconductor    Analog mixed-signal IC   
File Size645KB,14 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance  
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87339AMI-11LF Overview

IC clk gen 3.3V lvpecl 20-soic

87339AMI-11LF Parametric

Parameter NameAttribute value
Datasheets
ICS87339I-11
Product Photos
20-SOIC 0.295
PCN Design/Specificati
Assembly Lot Number Scheme 12/Oct/2013
Standard Package37
CategoryIntegrated Circuits (ICs)
FamilyClock/Timing - Clock Generators, PLLs, Frequency Synthesizers
PackagingTube
TypeClock Gene
PLLN
InpuHCSL, LVDS, LVHSTL, LVPECL, SSTL
OutpuLVPECL
Number of Circuits1
Ratio - InpuOutpu
Differential - InpuOutpu
Frequency - Max1GHz
Divider/MultiplieYes/N
Voltage - Supply3 V ~ 3.6 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mou
Package / Case20-SOIC (0.295", 7.50mm Width)
Supplier Device Package20-SOIC
Other NamesICS87339AMI-11LFICS87339AMI-11LF-ND
L
OW
S
KEW
,
÷2/4,÷4/5/6,
D
IFFERENTIAL
-
TO
-3.3V LVPECL C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS87339I-11 is a low skew, high perfor-
mance Differential-to-3.3V LVPECL Clock Gen-
HiPerClockS™
erator/Divider and a member of the HiPerClockS™
family of High Performance Clock Solutions
from IDT. The ICS87339I-11 has one differen-
tial clock input pair. The CLK, nCLK pair can accept most
standard differential input levels. The clock enable is
internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the
clock enable pin.
ICS87339I-11
F
EATURES
Dual ÷2, ÷4 differential 3.3V LVPECL outputs;
Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs
One differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum clock input frequency: 1GHz
Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
Output skew: 35ps (maximum)
Part-to-part skew: 385ps (maximum)
Bank skew: Bank A - 20ps (maximum)
Bank B - 20ps (maximum)
Propagation delay: 2.1ns (maximum)
LVPECL mode operating voltage supply range:
V
CC
= 3V to 3.6V, V
EE
= 0V
Available in both standard (RoHS5) and lead-free (RoHS 6)
packages
ICS
Guaranteed output and part-to-part skew characteristics
make the ICS87339I-11 ideal for clock distribution applica-
tions demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
DIV_SELA
QA0
nQA0
nCLK_EN
D
Q
LE
CLK
nCLK
÷2, ÷4
P
IN
A
SSIGNMENT
V
CC
nCLK_EN
DIV_SELB0
CLK
nCLK
RESERVED
MR
V
CC
DIV_SELB1
DIV_SELA
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
V
EE
R
QA1
nQA1
QB0
nQB0
÷4, ÷5, ÷6
ICS87339I-11
20-Lead TSSOP
6.50mm x 4.40mm x 0.92 package body
G Package
Top View
20-Lead SOIC, 300MIL
7.5mm x 12.8mm x 2.25mm package body
M Package
Top View
R
MR
DIV_SELB0
DIV_SELB1
QB1
nQB1
87339AGI-11
1
REV. A
March 3,
2009

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