÷1, ÷2 DIFFERENTIAL-TO-LVPECL CLOCK GENERATOR
ICS87321I
G
ENERAL
D
ESCRIPTION
The ICS87321I is a high perfor mance ÷1, ÷2
Differential-to-LVPECL Clock Generator and a mem-
HiPerClockS™
ber of the HiPerClockS™ family of High Performance
Clock Solutions from IDT. The CLK, nCLK pair can
accept most standard differential input levels. The
ICS87321I is characterized to operate from a 3.3V or 2.5V power
supply. Guaranteed part-to-part skew characteristics make the
ICS87321I ideal for those clock distribution applications demand-
ing well defined performance and repeatability.
F
EATURES
• One differential LVPECL output
• One CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum clock input frequency: 700MHz
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
• Part-to-part skew: 600ps (maximum)
• Propagation delay: 1.8ns (maximum)
• Additive phase Jitter, RMS: 0.18ps
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
B
LOCK
D
IAGRAM
CLK
Pulldown
nCLK
Pullup
÷1
0
1
Q
nQ
P
IN
A
SSIGNMENT
CLK
nCLK
MR
F_SEL
1
2
3
4
8
7
6
5
Vcc
Q
nQ
V
EE
R ÷2
MR
Pulldown
ICS87321I
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
F_SEL
Pulldown
IDT
™
/ ICS
™
3.3V LVPECL CLOCK GENERATOR
1
ICS87321AMI REV. A APRIL 7, 2009
ICS87321I
÷1, ÷2 DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
Name
CLK
nCLK
MR
Input
Input
Input
Type
Pullup
Description
Pulldown Non-inver ting differential clock input.
Inver ting differential clock input.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (Q) to go low and the inver ted outputs
Pulldown
(nQ) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels. See Table 3.
Selects divider value for Q, nQ outputs as described in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Positive supply pin.
4
5
6, 7
8
F_SEL
V
EE
nQ, Q
V
CC
Input
Power
Output
Power
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. F
UNCTION
T
ABLE
MR
1
0
0
F_SEL
X
0
1
Divide Value
Reset: Q output low, nQ output high
÷1
÷2
IDT
™
/ ICS
™
3.3V LVPECL CLOCK GENERATOR
2
ICS87321AMI REV. A APRIL 7, 2009
ICS87321I
÷1, ÷2 DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5 V
50mA
100mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
95°C/W (0 lfpm)
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
18
Units
V
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.5V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
16
Units
V
mA
T
ABLE
4C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%
OR
2.5V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol Parameter
V
IH
V
IL
V
HYS
I
IH
I
IL
Input High Voltage
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= 3.3V
V
CC
= 2.5V
MR, F_SEL
MR, F_SEL
MR, F_SEL
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V, or 2.625V V
IN
= 0V
-5
Minimum
2
1.7
-0.3
-0.3
100
150
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
Units
V
V
V
V
mV
µA
µA
Input Low Voltage
Input Hysteresis
Input High Current
Input Low Current
T
ABLE
4D. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%
OR
2.5V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
Test Conditions
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V, or 2.625V V
IN
= 0V
-5
-150
0.15
V
EE
+ 0.5
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
nCLK
V
CC
= 3.465V or 2.625V, V
IN
= 0V
Peak-to-Peak Input Voltage;
V
PP
NOTE 1
Common Mode Input Voltage;
V
CMR
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
IDT
™
/ ICS
™
3.3V LVPECL CLOCK GENERATOR
3
ICS87321AMI REV. A APRIL 7, 2009
ICS87321I
÷1, ÷2 DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
T
ABLE
4E. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol Parameter
V
OH
V
OL
V
SWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.65
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
4E. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.5V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol Parameter
V
OH
V
OL
V
SWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.4
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.5
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
f
CLK
Parameter
Clock Input Frequency
Propagation Delay; CLK to
NOTE 1
Q (Dif)
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
Test Conditions
Minimum
Typical
Maximum
700
1.2
155.52MHz, Integration Range:
(12kHz - 20MHz)
0.18
600
20% to 80%
100
600
1.8
Units
MHz
ns
ps
ps
ps
t
PD
t
jit
t
sk(pp)
t
R
/ t
F
odc
Output Duty Cycle; NOTE 4
48
53
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Input duty cycle must be 50%.
IDT
™
/ ICS
™
3.3V LVPECL CLOCK GENERATOR
4
ICS87321AMI REV. A APRIL 7, 2009
ICS87321I
÷1, ÷2 DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
T
ABLE
5B. AC C
HARACTERISTICS
,
V
CC
= 2.5V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
f
CLK
Parameter
Clock Input Frequency
Propagation Delay; CLK to
NOTE 1
Q (Dif)
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
Test Conditions
Minimum
Typical
Maximum
700
1.2
155.52MHz, Integration Range:
(12kHz - 20MHz)
0.18
600
20% to 80%
100
600
1.8
Units
MHz
ns
ps
ps
ps
t
PD
t
jit
t
sk(pp)
t
R
/ t
F
odc
Output Duty Cycle; NOTE 4
45
55
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Input duy cycle must be 50%.
IDT
™
/ ICS
™
3.3V LVPECL CLOCK GENERATOR
5
ICS87321AMI REV. A APRIL 7, 2009
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