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MC100ES6039EG

Description
IC clk generation chip 20-soic
Categorysemiconductor    Analog mixed-signal IC   
File Size291KB,9 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance  
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IC clk generation chip 20-soic

MC100ES6039EG Parametric

Parameter NameAttribute value
Datasheets
MC100ES6039
Product Photos
20-SOIC 0.295
Standard Package37
CategoryIntegrated Circuits (ICs)
FamilyClock/Timing - Clock Generators, PLLs, Frequency Synthesizers
PackagingTube
TypeClock Gene
PLLN
InpuECL, HSTL, LVDS, PECL
OutpuECL, PECL
Number of Circuits1
Ratio - InpuOutpu
Differential - InpuOutpu
Frequency - Max1GHz
Divider/MultiplieYes/N
Voltage - Supply3.135 V ~ 3.8 V
Operating Temperature0°C ~ 70°C
Mounting TypeSurface Mou
Package / Case20-SOIC (0.295", 7.50mm Width)
Supplier Device Package20-SOIC
3.3V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/6
Clock Generation Chip
Product Discontinuance Notice – Last Time Buy Expires on (12/19/2013)
The MC100ES6039 is a low skew
2/4, 4/6
clock generation chip designed explicitly
for low skew clock generation applications. The internal dividers are synchronous to each
other, therefore, the common output edges are all precisely aligned. The device can be
driven by either a differential or single-ended ECL or, if positive power supplies are used,
LVPECL input signals. In addition, by using the V
BB
output, a sinusoidal source can be AC
coupled into the device.
The common enable (EN) is synchronous so that the internal dividers will only be
enabled/disabled when the internal clock is already in the LOW state. This avoids any
chance of generating a runt clock pulse on the internal clock when the device is enabled/
disabled as can happen with an asynchronous control. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore, all associated specification limits
are referenced to the negative edge of the clock input.
Upon startup, the internal flip-flops will attain a random state; therefore, for systems
which utilize multiple ES6039s, the master reset (MR) input must be asserted to ensure
synchronization. For systems which only use one ES6039, the MR pin need not be
exercised as the internal divider design ensures synchronization between the
2/4
and the
4/6
outputs of a single device. All V
CC
and V
EE
pins must be externally connected to
power supply to guarantee proper operation.
The 100ES Series contains temperature compensation.
Features
Maximum Frequency >1.0 GHz Typical
50 ps Output-to-Output Skew
PECL Mode Operating Range: V
CC
= 3.135 V to 3.8 V with V
EE
= 0 V
ECL Mode Operating Range: V
CC
= 0 V with V
EE
= –3.135 V to –3.8 V
Open Input Default State
Synchronous Enable/Disable
Master Reset for Synchronization of Multiple Chips
V
BB
Output
LVDS and HSTL Input Compatible
20-Lead Pb-Free Package Available
MC100ES6039
DATASHEET
DW SUFFIX
20-LEAD SOIC PACKAGE
CASE 751D-07
EG SUFFIX
20-LEAD SOIC PACKAGE
Pb-FREE PACKAGE
CASE 751D-07
ORDERING INFORMATION
Device
MC100ES6039DW
MC100ES6039DWR2
MC100ES6039EG
MC100ES6039EGR2
Package
SO-20
SO-20
SO-20 (Pb-Free)
SO-20 (Pb-Free)
MC100ES6039 REVISION 3 FEBRUARY 5, 2013
1
©2013 Integrated Device Technology, Inc.

MC100ES6039EG Related Products

MC100ES6039EG
Description IC clk generation chip 20-soic
Standard Package 37
Category Integrated Circuits (ICs)
Family Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers
Packaging Tube
Type Clock Gene
PLL N
Inpu ECL, HSTL, LVDS, PECL
Outpu ECL, PECL
Number of Circuits 1
Ratio - Inpu Outpu
Differential - Inpu Outpu
Frequency - Max 1GHz
Divider/Multiplie Yes/N
Voltage - Supply 3.135 V ~ 3.8 V
Operating Temperature 0°C ~ 70°C
Mounting Type Surface Mou
Package / Case 20-SOIC (0.295", 7.50mm Width)
Supplier Device Package 20-SOIC
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