PRELIMINARY
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-
SSTL_2 FREQUENCY SYNTHESIZER
ICS848004I
Features
•
•
•
•
•
•
Four SSTL_2 differential clock output pairs
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended clock input
Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, 53.125MHz
VCO range: 560MHz – 680MHz
RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637kHz – 10MHz): 0.80ps (typical)
SSTL operating voltage supply ranges:
V
DD
/ V
DDO
3.0V – 3.6V / 3.0V to 3.6V
2.3V – 3.6V / 2.3V – 2.7V
2.3V – 3.6V / 1.7V – 1.9V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
General Description
The ICS848004I is a 4 output SSTL_2 Synthesizer
ICS
optimized to generate Fibre Channel reference clock
HiPerClockS™
frequencies and is a member of the HiPerClocks
TM
family of high performance clock solutions from IDT.
Using a 26.5625MHz 18pF parallel resonant crystal,
the following frequencies can be generated based on the 2 fre-
quency select pins (F_SEL[1:0]): 212.5MHz, 187.5MHz,
159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz. The
ICS848004I uses IDT’s 3
rd
generation low phase noise VCO
technology and can achieve 1ps or lower typical rms phase jitter,
easily meeting Fibre Channel jitter requirements. The ICS848004I
is packaged in a small 24-pin TSSOP package.
•
•
Frequency Select Function Table
Inputs
Input Frequency (MHz)
26.5625
26.5625
26.5625
26.5625
26.04166
23.4375
F_SEL1
0
0
1
1
0
0
F_SEL0
0
1
0
1
1
0
M Div. Value
24
24
24
24
24
24
N Div. Value
3
4
6
12
4
3
M/N Div. Value
8
6
4
2
6
8
Output Frequency (MHz)
212.5
159.375
106.25
53.125
156.25
187.5
Block Diagram
F_SEL[1:0]
Pulldown
nPLL_SEL
Pulldown
F_SEL[1:0]
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
2
Q0
1
nQ0
Q1
nQ1
Pin Assignment
nQ1
Q1
V
DDO
Q0
nQ0
MR
nPLL_SEL
nc
V
DDA
F_SEL0
V
DD
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
V
DDO
Q3
nQ3
GND
nc
nXTAL_SEL
TEST_CLK
GND
XTAL_IN
XTAL_OUT
TEST_CLK
Pulldown
26.5625MHz
1
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL
Pulldown
0
Phase
Detector
VCO
637.5MHz
(w/26.5625MHz
Reference)
0
Q2
nQ2
ICS848004I
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
M = 24 (fixed)
Q3
nQ3
MR
Pulldown
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™
SSTL_2 FREQUENCY SYNTHESIZER
1
ICS848004AGI REV. B MAY 8, 2008
ICS848004I
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-SSTL_2 FREQUENCY SYNTHESIZER
PRELIMINARY
Table 1. Pin Descriptions
Number
1, 2
3, 22
4, 5
Name
nQ1, Q1
V
DDO
Q0, nQ0
Output
Power
Output
Type
Description
Differential output pair. SSTL_2 interface levels.
Output supply pins.
Differential output pair. SSTL_2 interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go LOW and the inverted outputs nQx to go
HIGH. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Selects between the PLL and TEST_CLK as input to the dividers. When
LOW, selects PLL (PLL enabled). When HIGH, deselects the reference clock
(PLL bypassed). LVCMOS/LVTTL interface levels.
No connect.
Analog supply pin.
Pulldown
Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
Parallel resonant crystal interface.
XTAL_OUT is the output, XTAL_IN is the input.
Power supply ground.
Pulldown
Pulldown
Single-ended test clock input. LVCMOS/LVTTL interface levels.
Selects between the single-ended TEST_CLK or crystal interface as the PLL
reference source. When HIGH, selects TEST_CLK. When LOW, selects
crystal inputs. LVCMOS/LVTTL interface levels.
Differential output pair. SSTL_2 interface levels.
Differential output pair. SSTL_2 interface levels.
6
MR
Input
Pulldown
7
8, 18
9
10, 12
11
13,
14
15, 19
16
17
20, 21
23, 24
nPLL_SEL
nc
V
DDA
F_SEL0.
F_SEL1
V
DD
XTAL_OUT,
XTAL_IN
GND
TEST_CLK
nXTAL_SEL
nQ3, Q3
Q2, nQ2
Input
Unused
Power
Input
Power
Input
Power
Input
Input
Output
Output
Pulldown
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
Ω
IDT™ / ICS™
SSTL_2 FREQUENCY SYNTHESIZER
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ICS848004AGI REV. B MAY 8, 2008
ICS848004I
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-SSTL_2 FREQUENCY SYNTHESIZER
PRELIMINARY
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD O
+ 0.5V
82.3°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 10%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.97
2.97
2.97
Typical
3.3
3.3
3.3
65
7
12
Maximum
3.63
3.63
3.63
Units
V
V
V
mA
mA
mA
Table 3B. Power Supply DC Characteristics,
V
DD
= 3.3V ± 10% or 2.5V ± 10%, V
DDO
= 2.5V ± 10%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.25
2.25
2.25
Typical
3.3
3.3
2.5
64
7
12
Maximum
3.63
3.63
2.75
Units
V
V
V
mA
mA
mA
IDT™ / ICS™
SSTL_2 FREQUENCY SYNTHESIZER
3
ICS848004AGI REV. B MAY 8, 2008
ICS848004I
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-SSTL_2 FREQUENCY SYNTHESIZER
PRELIMINARY
Table 3C. Power Supply DC Characteristics,
V
DD
= 3.3V ± 10% or 2.5V ± 10%, V
DDO
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.25
2.25
1.71
Typical
3.3
3.3
1.8
62
7
12
Maximum
3.63
3.63
1.89
Units
V
V
V
mA
mA
mA
Table 3D. LVCMOS/LVTTL DC Characteristics,
T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
Input Low Voltage
TEST_CLK,
MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
TEST_CLK,
MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
V
DD
= 3.3V
V
DD
= 2.5V
Input
High Current
Input
Low Current
V
DD
= V
IN
= 3.63V or
2.75V
V
DD
= 3.63V or 2.75V,
V
IN
= 0V
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
V
IL
I
IH
I
IL
-5
µA
Table 3E. Differential DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 10%, T
A
= -40°C to 85°C
Symbol
V
OD
V
PP
V
CMR
V
OH
V
OL
Parameter
Output Differential Voltage
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1
Output High Voltage; NOTE 2
Output Low Voltage; NOTE 2
Test Conditions
Minimum
0.7
0.15
0.5
>2.1
<0.9
1.3
V
DDO
– 0.85
Typical
Maximum
Units
V
V
V
V
V
NOTE 1: V
CMR
, V
PP
defined for driving TEST_CLK input with differential levels other than SSTL_2.
NOTE 2: Outputs termination with 50
Ω
to GND.
IDT™ / ICS™
SSTL_2 FREQUENCY SYNTHESIZER
4
ICS848004AGI REV. B MAY 8, 2008
ICS848004I
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-SSTL_2 FREQUENCY SYNTHESIZER
PRELIMINARY
Table 3F. Differential DC Characteristics,
V
DD
= 3.3V ± 10% or 2.5V ± 10%, V
DDO
= 2.5V ± 10%, T
A
= -40°C to 85°C
Symbol
V
OD
V
PP
V
CMR
V
OH
V
OL
Parameter
Output Differential Voltage
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1
Output High Voltage; NOTE 2
Output Low Voltage; NOTE 2
Test Conditions
Minimum
0.7
0.15
0.5
>1.77
<0.73
1.3
V
DDO
– 0.85
Typical
Maximum
Units
V
V
V
V
V
NOTE 1: V
CMR
, V
PP
defined for driving TEST_CLK input with differential levels other than SSTL_2.
NOTE 2: Outputs termination with 50
Ω
to GND.
Table 3G. Differential DC Characteristics,
V
DD
= 3.3V ± 10% or 2.5V ± 10%, V
DDO
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
PP
V
CMR
V
OH
V
OL
Parameter
Output Differential Voltage
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1
Output High Voltage; NOTE 2
Output Low Voltage; NOTE 2
Test Conditions
Minimum
0.7
0.15
0.5
>1.19
<0.615
1.3
V
DDO
– 0.85
Typical
Maximum
Units
V
V
V
V
V
NOTE 1: V
CMR
, V
PP
defined for driving TEST_CLK input with differential levels other than SSTL_2.
NOTE 2: Outputs termination with 50
Ω
to GND.
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
23.33
Test Conditions
Minimum
Typical
Fundamental
26.5625
28.33
50
7
1
MHz
Maximum
Units
Ω
pF
mW
IDT™ / ICS™
SSTL_2 FREQUENCY SYNTHESIZER
5
ICS848004AGI REV. B MAY 8, 2008
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