PRELIMINARY
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-
LVDS/LVCMOS FREQUENCY SYNTHESIZER
ICS8440259-45
G
ENERAL
D
ESCRIPTION
The ICS8440259-45 is a 9 output synthesizer
optimized to generate Gigabit and 10 Gigabit
HiPerClockS™
Ether net clocks and is a member of the
HiPerClockS™family of high performance clock
solutions from IDT. Using a 25MHz, 18pF parallel
resonant crystal, the device will generate both 156.25MHz,
125MHz and 3.90625MHz clocks with mixed LVDS and
LVCMOS/LVTTL output levels. The ICS8440259-45 uses IDT’s
3
rd
generation low phase noise VCO technology and can
achieve <1ps typical rms phase jitter, easily meeting Ethernet
jitter requirements. The ICS8440259-45 is packaged in a small,
5mm x 5mm VFQFN package that is optimum for applications
with space limitations.
F
EATURES
•
One differential LVDS output at 156.25MHz or 125MHz
Four differential LVDS outputs at 125MHz
Three LVCMOS/LVTTL single-ended outputs at 125MHz
One LVCMOS/LVTTL single-ended output at 3.90625MHz
•
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input and PLL bypass from a single select pin
•
VCO range: 490MHz - 680MHz
•
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.42ps (typical)
•
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.45ps (typical)
•
LVDS supply voltage modes: full 3.3V and full 2.5V
•
LVCMOS supply voltage modes:
Core/Output Core/Output
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
•
0°C to 70°C ambient operating temperature
IC
S
B
LOCK
D
IAGRAM
nPLL_BYPASS
Pullup
F_SEL
Pulldown
•
Available in both standard (RoHS 5) and lead-free (RoHS6)
packages
REF_CLK
Pulldown
25MHz
0
0
Q0
nQ0
XTAL_IN
Phase
Detector
1
VCO
490-680MHz
÷5
÷4
1
OSC
XTAL_OUT
0
Q1
nQ1
Q2
nQ2
P
IN
A
SSIGNMENT
XTAL_OUT
REF_CLK
XTAL_IN
F_SEL
GND
V
DD
÷5
nPLL_BYPASS
1
÷25
V
DDA
Q3
nQ3
24
23
Q8
V
DDO
_
LVCMOS
Q7
GND
Q6
V
DDO
_
LVCMOS
Q5
GND
32 31 30 29 28 27 26 25
Q0
nQ0
GND
Q1
nQ1
V
DDO
_
LVDS
Q2
nQ2
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
V
DDO
_LVDS
GND
nQ4
GND
nQ3
V
DD
Q3
Q4
Q4
nQ4
Q5
ICS8440259-45
32-Lead VFQFN
5mm x 5mm x 0.75mm
package body
K Package
Top View
22
21
20
19
18
17
Q6
Q7
÷32
Q8
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
1
ICS8440259AK-45 REV. A MARCH 29, 2007
ICS8440259-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 9, 15,
17, 21, 32
4, 5
6, 12
7, 8
10, 11
13, 14
16, 2 7
18, 20,
2 2, 24
19, 23
25
26
28
Name
Q0, nQ0
GND
Q1, nQ1
V
DDO_LVDS
Q2, nQ2
Q3, nQ3
Q4, nQ4
V
DD
Q5, Q6,
Q7, Q8
V
DDO_LVCMOS
V
DDA
nPLL_BYPASS
F_SEL
Type
Output
Power
Output
Power
Output
Output
Output
Power
Output
Power
Power
Input
Input
Description
Differential clock outputs. LVDS interface levels.
Power supply ground.
Differential clock outputs. LVDS interface levels.
Output supply pins for Qx/nQx LVDS outputs.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Core supply pins.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output supply pins for Q5:Q8 LVCMOS outputs.
Analog supply pin.
Input select and PLL bypass control pin. See Table 3B.
Pullup
LVCMOS/LVTTL interface levels.
Pulldown Frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels.
29
REF_CLK
Input
Pulldown Single-ended LVCMOS/LVTTL reference clock input.
30,
XTAL_IN,
Crystal oscillator interface. XTAL_OUT is the output.
Input
31
XTAL_OUT
XTAL_IN is the input.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation
Capacitance
Input Pulldown Resistor
Output Impedance
Q5:Q8
V
DD,
V
DDO_LVCMOS
= 3.465V
V
DD,
V
DDO_LVCMOS
= 2.625V
V
DD
= 3.465, V
DDO_LVCMOS
= 2.625V
Test Conditions
Minimum
Typical
4
TBD
TBD
TBD
51
TBD
Maximum
Units
pF
pF
pF
pF
kΩ
Ω
T
ABLE
3A. F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
F_SEL
0
1
Input
Output Divider
÷5
÷4
Outputs
Q0/nQ0 Frequency
125MHz (default)
156.25MHz
T
ABLE
3B. PLL B
YPASS AND
I
NPUT
S
ELECT
F
UNCTION
T
ABLE
nPLL_BYPASS
0
1
Inputs
PLL Bypass
PLL Bypassed
PLL Enabled
Input Selected
REF_CLK
XTAL_IN/XTAL_OUT (default)
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
2
ICS8440259AK-45 REV. A MARCH 29, 2007
ICS8440259-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVCMOS)
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Operating Temperature Range, T
A
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
10mA
15mA
-40°C to +85°C
-65°C to 150°C
37°C/W (0 mps)
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO_LVCMOS
+ 0.5V
NOTE:
Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of
product at these conditions or any conditions beyond those listed
in the
DC Characteristics
or
AC Characteristics
is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO_LVCMOS
= V
DDO_LVDS
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO_LVCMOS,
V
DDO_LVDS
I
DD
I
DDA
I
DDO_LVCMOS,
I
DDO_LVDS
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Power Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.10
3.135
Typical
3.3
3.3
2.5
108
10
160
Maximum
3.465
V
DD
3.465
Units
V
V
V
mA
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO_LVCMOS
= 2.5V ± 5%,T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO_LVCMOS
I
DD
I
DDA
I
DDO_LVCMOS
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Power Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.10
2.375
Typical
3.3
3.3
2.5
105
10
145
Maximum
3.465
V
DD
2.625
Units
V
V
V
mA
mA
mA
T
ABLE
3C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO_LVCMOS
= V
DDO_LVDS
= 2.5V ± 5%,T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO_LVCMOS,
V
DDO_LVDS
I
DD
I
DDA
I
DDO_LVCMOS,
I
DDO_LVDS
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Power Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.10
2.375
Typical
2.5
2.5
2.5
72
10
100
Maximum
2.625
V
DD
2.625
Units
V
V
V
mA
mA
mA
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
3
ICS8440259AK-45 REV. A MARCH 29, 2007
ICS8440259-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
4D. LVCMOS/LVTTL DC C
HARACTERISTICS
,
T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
V
IL
I
IH
Input High Voltage
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
REF_CLK
nPLL_BYPASS
REF_CLK
I
IL
Input Low Current
nPLL_BYPASS
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
-5
-150
Minimum Typical
2
1.7
-0.3
-0.3
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
15 0
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
0.5
V
Input Low Voltage
Input High Current
Output
2.1
Q5:Q8
V
DDO_LVCMOS
= 3.3V±5%
High Voltage;
V
OH
1.75
Q5:Q8
V
DDO_LVCMOS
= 2.5V±5%
NOTE 1
Output
V
OL
Low Voltage;
Q5:Q8
V
DDO_LVCMOS
= 3.3V or 2.5V±5%
NOTE 1
NOTE 1: Outputs terminated with 50
Ω
to V
DDO_LVCMOS
/2. See Parameter Measurement Information,
Output Load Test Circuit diagram.
T
ABLE
4E. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDO_LVDS
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
250
Typical
325
25
1.35
25
Maximum
450
Units
mV
mV
V
mV
T
ABLE
4F. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDO_LVDS
= 2.5V ± 5%,T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
250
Typical
315
25
1.25
25
Maximum
450
Units
mV
mV
V
mV
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
4
ICS8440259AK-45 REV. A MARCH 29, 2007
ICS8440259-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant cr ystal.
Test Conditions
Minimum
Typical
25
50
7
1
Maximum
Units
MHz
Ω
pF
mW
Fundamental
T
ABLE
6A. AC C
HARACTERISTICS
,
V
DD
= V
DDO_LVCMOS
= V
DDO_LVDS
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol
Parameter
Q0/nQ0:Q4/nQ4
f
OUT
Output
Frequency
Q5:Q7
Q8
Q0/nQ0
RMS Phase Jitter
(Random);
NOTE 1
Q0:4/nQ0:4
Q0/nQ0
Q5:Q7
Q0/nQ0:Q4/nQ4
t
R
/ t
F
Output
Rise/Fall Time
Q0/nQ0
Q5:Q7
Q8 (NOTE 2)
Q0/nQ0:Q4/nQ4
Q0/nQ0
Q5:Q7
Q8
Q0/nQ0:Q4/nQ4
Output
Q0/nQ0
odc
Duty Cycle,
Q5:Q7
BYPASS Mode
Q8
NOTE 1: Please refer to the Phase Noise Plots.
NOTE 2: Output loaded with 15pF.
odc
Output
Duty Cycle
125MHz, (1.875MHz - 20MHz)
156.25MHz,
(1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
125MHz, 20% to 80%
156.25MHz, 20% to 80%
125MHz, 20% to 80%
3.90625MHz, 20% to 80%
125MHz
156.25MHz
125MHz
3.90625MHz
125MHz
156.25MHz
125MHz
3.90625MHz
45
45
45
45
Test Conditions
Minimum
Typical
125
125
3.90625
156.25
0.41
0.45
0.45
375
335
950
1
47
50
46
50
TBD
TBD
TBD
TBD
550
550
1.2
20
55
55
55
55
Maximum
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ns
%
%
%
%
%
%
%
%
t
jit(Ø)
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
5
ICS8440259AK-45 REV. A MARCH 29, 2007
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