PECL/LVDS/CMOS OUTPUT SMD
CRYSTAL CLOCK OSCILLATOR
ALD SERIES
Pb
RoHS
Compliant
5.0 x 7.0 x 1.8mm
| | | | | | | | | | | | | | |
FEATURES:
• Based on a proprietary digital multiplier
• 2.5V to 3.3V +/- 5% operation
• Tri-State Output
• Ceramic SMD, low profile package
• Low Phase Noise and Jitter
•
156.25MHz, 187.5MHz, and 212.5MHz applications
APPLICATIONS:
• SONET, xDSL
• SDH, CPE
• STB
STANDARD SPECIFICATIONS:
PARAMETERS
ABRACON P/N:
Frequency range:
Operating temperature:
Storage temperature:
Overall frequency stability:
Supply voltage (Vdd):
Jitter:
Low Phase Noise:
ALD Series
750 kHz to 800 MHz
0° C to + 70° C (see options)
- 55° C to + 125° C
± 50 ppm max. (see options)
3.3V ±10% (see options)
RMS phase jitter 3ps typ., <5ps max. (12KHz - 20MHz)
Period jitter peak to peak ,35ps typical
-109 dBc/Hz @ 1kHz Offset from 622.08MHz
-110 dBc/Hz @ 10kHz Offset from 622.08MHz
-109 dBc/Hz @ 100KHz Offset from 622.08MHz
-112 dBc/Hz @ 1kHz Offset from 155.52MHz
-125 dBc/Hz @ 10kHz Offset from 155.52MHz
-123 dBc/Hz @ 100KHz Offset from 155.52MHz
"1" (V
IH
≥ 0.7*Vdd) or open: Oscillation
"0" (V
IL
< 0.3*Vdd): No Oscillation / Hi Z
Tristate Function:
PECL:
Supply current (I
DD
):
65mA max (for 750kHz < Fo < 96MHz), 100mA max (96MHz ≤ Fo < 800MHz)
Output Logic High:
V
dd
-1.025V min, V
dd
-0.880V max.
Output Logic Low:
V
dd
-1.810V min. V
dd
-1.620V max.
Symmetry (Duty Cycle):
45% min, 50% typ, 55% max,
Rise time:
0.85ns
Fall time:
0.85ns
Supply current (I
DD
):
65mA max (for 750kHz < Fo < 96MHz), 100mA max (96MHz ≤ Fo < 800MHz)
Output Clock Duty Cycle @ 1.25V:
45% min, 50% typical, 55% max
Output Differential Voltage (V
OD
):
247mV min, 355mV typical, 454mV max
VDD Magnitude Change ( V
OD
):
-50mV min, 50mV max
Output High Voltage :
V
OH
= 1.4V typical, 1.6V max.
Output Low Voltage :
V
OL
= 0.9V min, 1.1V typical
Offset Voltage [R
L
= 100
]:
V
OS
= 1.125V min, 1.2V typical, 1.375V max
Offset Magnitude Change [R
L
= 100
]:
V
OS
= 0mV min, 3mV typical, 25mV max
Power-off Leakage (I
OXD
) [Vout=VDD or GND, VDD=0V] =
±1 A typical, ±10 A max.
Differential Clock Rise Time (t
r
) [R
L
=100 , CL=10pF]:
0.2nS min, 0.7nS typical, 1.0nS,max
Differential Clock Fall Time (t
f
) [R
L
=100 , CL=10pF]:
0.2nS min, 0.7nS typical, 1.0nS max
Supply current (I
DD
):15mA
max (for 750kHz < Fo < 24MHz), 30mA max (for 24MHz ≤ Fo < 96MHz),
65mA max (96MHz ≤ Fo < 800MHz)
Output Clock Rise/ Fall Time [10%~90% VDD with 10pF load]:
5.0ns max (for 750kHz < Fo < 24MHz)
5.0ns max (for 24MHz ≤ Fo < 800MHz)
Output Clock Duty Cycle [Measured @ 50% VDD]:
45% min, 50% typical, 55% max
LVDS
CMOS:
ABRACON IS
ISO9001:2008
CERTIFIED
Revised: 05.20.10
30332 Esperanza, Rancho Santa Margarita, California 92688
tel 949-546-8000
|
fax 949-546-8001
| www.abracon.com
Visit www.abracon.com for Terms & Conditions of Sale
PECL/LVDS/CMOS OUTPUT SMD
OSCILLATOR
CERAMIC SMD CRYSTAL CLOCK
CLOCK OSCILLATOR
CRYSTAL
ALD SERIES
Pb
RoHS
Compliant
5.0 x 7.0 x 1.8mm
| | | | | | | | | | | | | | |
TAPE AND REEL:
T= tape and reel (1,000pcs/reel)
Dimension : mm
REFLOW PROFILE:
NOTE:
Abracon manufactured products are intended for general commercial and industrial use. For applications requiring high
reliability and/or presenting extreme operating environment, written consent & authorization from Abracon is required.
ABRACON IS
ISO9001:2008
CERTIFIED
Revised: 05.14.10
30332 Esperanza, Rancho Santa Margarita, California 92688
tel 949-546-8000
|
fax 949-546-8001
| www.abracon.com
Visit www.abracon.com for Terms & Conditions of Sale
Embedded System
京公网安备 11010802033920号
EEWORLD
