XC6SLX150T-2FG676I datasheet, PDF

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XC6SLX150T-2FG676I: DescriptionIC fpga 396 I/O 676fcbga; CategoryProgrammable logic devices Programmable logic; File Size964KB，16 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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XC6SLX150T-2FG676I Overview

IC fpga 396 I/O 676fcbga

XC6SLX150T-2FG676I Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	27 X 27 MM, 1 MM PITCH, FBGA-676
Contacts	676
Reach Compliance Code	_compli
ECCN code	3A991.D
Factory Lead Time	12 weeks
maximum clock frequency	667 MHz
Combined latency of CLB-Max	0.26 ns
JESD-30 code	S-PBGA-B676
JESD-609 code	e0
length	27 mm
Humidity sensitivity level	3
Configurable number of logic blocks	11519
Number of entries	396
Number of logical units	147443
Output times	396
Number of terminals	676
Maximum operating temperature	100 °C
Minimum operating temperature	-40 °C
organize	11519 CLBS
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA676,26X26,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
power supply	1.2,2.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	2.44 mm
Maximum supply voltage	1.26 V
Minimum supply voltage	1.14 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	27 mm
Base Number Matches	1

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1300 Henley Court

Pullman, WA 99163

509.334.6306

www.digilentinc.com

Anvyl™ FPGA Board Reference Manual

Revised April 11, 2016

This manual applies to the Anvyl rev. B

Overview

The Anvyl FPGA development platform is a

complete, ready-to-use digital circuit

development platform based on a speed grade

-3 Xilinx Spartan-6 LX45 FPGA. The large FPGA,

along with the 100-mbps Ethernet, HDMI

Video, 128MB DDR2 memory, 4.3" LED backlit

LCD touchscreen, 128x32 pixel OLED display,

630 tie-point breadboard, multiple USB HID

controllers, and I

S audio codec, makes the

Anvyl an ideal platform for an FPGA learning

station capable of supporting embedded

processor designs based on Xilinx's

MicroBlaze. The Anvyl is compatible with all

Xilinx CAD tools, including ChipScope, EDK,

and the free ISE WebPACK™, so designs can be

completed at no extra cost. The board

dimensions are 27.5cm x 21cm.

The Spartan-6 LX45 is optimized for high

performance logic and offers:



6,822 slices, each containing four

input LUTs and eight flip-flops

2.1Mbits of fast block RAM

four clock tiles (eight DCMs & four

PLLs)

58 DSP slices

500MHz+ clock speeds

The Anvyl board.

A comprehensive collection of board support

IP and reference designs, and a large collection

of add-on boards are available on the Digilent

website. See the Anvyl page at

www.digilentinc.com for more information.

DOC#: 502-258

Other product and company names mentioned may be trademarks of their respective owners.

Page

Anvyl™ FPGA Board Reference Manual

Features include:



Spartan6-LX45 FPGA：XC6SLX45-CSG484-3

128MB DDR2 SDRAM

2MB SRAM

16MB QSPI FLASH for configuration and data storage

10/100 Ethernet PHY

HDMI Video Output

12-bit VGA port

4.3" wide-format vivid color LED backlit LCD screen

128x32 pixel 0.9'' WiseChip/Univision UG-23832HSWEG04 OLED graphic display panel

three two-digit Seven Segment LED displays

S Audio codec with line-in, line-out, mic, and headphone

100MHz Crystal Oscillator

on-board USB2 ports for programming and USB-HID devices (for mouse/keyboard)

Digilent USB-JTAG circuitry with USB-UART functionality

keypad with 16 labeled keys (0-F)

GPIO: 14 LEDs (10 red, 2 yellow, 2 green), 8 slide switches, 8 DIP switches in 2 groups and 4 push buttons

breadboard with 10 Digital I/O's

32 I/O's routed to 40-pin expansion connector (I/O's are shared with Pmod ports)

seven 12-pin Pmod ports with 56 I/O's total

ships with a 20W power supply and USB cable

FPGA Configuration

After being turned on, the FPGA on the Anvyl board must be configured (or programmed) before it can perform

any functions. The FPGA can be configured in three ways: a PC can use the Digilent USB-JTAG circuitry (port J12,

labeled "PROG") to program the FPGA any time power is on, a configuration file stored in the onboard SPI Flash

ROM can be automatically transferred to the FPGA at power-on, or a programming file can be transferred from a

USB memory stick to the USB HID port labeled "Host" (J14).

An on-board mode jumper (JP2) selects between JTAG/USB and ROM programming modes. If JP2 is not loaded, the

FPGA will automatically configure itself from the ROM. If JP2 is loaded, the FPGA will remain idle after power-on

until configured from the JTAG or Serial programming port (USB memory stick).

Both Digilent and Xilinx freely distribute software that can be used to program the FPGA and the SPI ROM.

Programming files are stored within the FPGA in SRAM-based memory cells. This data defines the FPGA's logic

functions and circuit connections, and it remains valid until it is erased by removing power, asserting the PROG_B

input, or until it is overwritten by a new configuration file.

FPGA configuration files transferred via the JTAG port and from a USB stick use the .bit file type, and SPI

programming files use the .mcs file type. Xilinx's ISE WebPack and EDK software can create .bit files from VHDL,

Verilog, or schematic-based source files (EDK is used for MicroBlaze™ embedded processor based designs). Once a

.bit file has been created, the Anvyl's FPGA can be programmed with it over the USB-JTAG circuitry (port J12) using

either Digilent's Adept software or Xilinx's iMPACT software. To generate a .mcs file from a .bit file, use the PROM

File Generator tool within Xilinx's iMPACT software. The .mcs file can then be programmed to the SPI Flash using

iMPACT.

Other product and company names mentioned may be trademarks of their respective owners.

Page

Anvyl™ FPGA Board Reference Manual

The FPGA can also be programmed from a FAT formatted memory stick attached to the USB-HID HOST port (J14) if

the stick contains a single .bit configuration file in the root directory, JP2 is loaded, and board power is cycled. The

FPGA will automatically reject any .bit files that are not built for the proper FPGA.

Power Supplies

The Anvyl board requires an external 5V, 4A or greater power source with a center positive, 2.1mm internal

diameter coax plug (a suitable supply is provided as part of the Anvyl kit). Voltage regulator circuits from Analog

Devices create the required 3.3V, 1.8V and 1.2V supplies from the main 5V supply. A power-good LED (LD19),

driven by the wired OR of all the power-good outputs on the supplies, indicates that all supplies are operating

normally. The following devices are present on each rail:



5V : USB-HID connectors, TFT touchscreen controller, HDMI, and expansion connector

3.3V : SRAM, Ethernet PHY I/O, USB-HID controllers, FPGA I/O, oscillators, SPI Flash, Audio codec, TFT

display, OLED display, GPIO, Pmods, and expansion connector

1.8V : DDR2, USB-JTAG/USB-UART controller, FPGA I/O, and GPIO

1.2V : FPGA core and Ethernet PHY core

Adept System

Adept has a simplified configuration interface. To program the Anvyl board using Adept, first set up the board and

initialize the software:



plug in and attach the power supply

plug in the USB cable to the PC and to the USB PROG port on the board

start the Adept software

turn ON Anvyl's power switch

wait for the FPGA to be recognized

Use the browse function to associate the desired .bit file with the FPGA, and click on the Program button. The

configuration file will be sent to the FPGA, and a dialog box will indicate whether programming was successful. The

configuration "done" LED will light up after the FPGA has been successfully configured. Before starting the

programming sequence, Adept ensures that any selected configuration files contain the correct FPGA ID code –

this prevents incorrect .bit files from being sent to the FPGA. In addition to the navigation bar and browse and

program buttons, the configuration interface provides an Initialize Chain button, console window, and status bar.

The Initialize Chain button is useful if USB communications with the board have been interrupted. The console

window displays current status, and the status bar shows real-time progress when downloading a configuration

file.

DDR2 Memory

A single 1Gbit DDR2 memory chip is driven from the memory controller block in the Spartan-6 FGPA. The DDR2

device, a MT47H64M16HR-25E or equivalent, provides a 16-bit bus and 64M locations. The Anvyl board has been

tested for DDR2 operation at up to an 800MHz data rate. The DDR2 interface follows the pin-out and routing

guidelines specified in the Xilinx Memory Interface Generator (MIG) User Guide. The interface supports SSTL18

Other product and company names mentioned may be trademarks of their respective owners.

Page

Anvyl™ FPGA Board Reference Manual

signaling, and all address, data, clocks, and control signals are delay-matched and impedance-controlled. Two well-

matched DDR2 clock signal pairs are provided so the DDR can be driven with low-skew clocks from the FPGA.

Flash Memory

The Anvyl board uses a 128Mbit Numonyx N25Q128 Serial flash memory

device (organized as 16Mbit by 8) for non-volatile storage of FPGA

configuration files. The SPI Flash can be programmed with a .mcs file using

the iMPACT software. An FPGA configuration file requires less than 12Mbits,

leaving 116Mbits available for user data. Data can be transferred to and

from a PC to/from the flash device by user applications, or by facilities built

into the iMPACT PROM file generation software. User designs programmed

into the FPGA can also transfer data to and from the flash.

A board test/demonstration program is loaded into the SPI Flash during

manufacturing.

AB5

AB17

Y17

V13

W13

W17

CS#

SDI/DQ0

SDO/DQ1

WP#/DQ2

HLD#/DQ3

SCK

Spartan-6

SPI Flash

Figure 1. SPI flash interface.

Ethernet PHY

The Anvyl board includes an SMSC 10/100 mbps PHY (LAN8720A-CP-TR) paired with a Halo HFJ11-2450E RJ-45

connector. The PHY is connected to the FPGA using a RMII configuration. It is configured to boot into "All Capable,

with Auto Negotiation Enabled" mode on power-on. The data sheet for the SMSC PHY is available from the SMSC

website.

HDMI Output

The Anvyl board contains one unbuffered HDMI output port. The unbuffered port uses an HDMI type A connector.

Since the HDMI and DVI systems use the same TMDS signaling standard, a simple adaptor (available at most

electronics stores) can be used to drive a DVI connector from the HDMI output port. The HDMI connector does not

include VGA signals, so analog displays cannot be driven.

The 19-pin HDMI connectors include four differential data channels, five GND connections, a one-wire Consumer

Electronics Control (CEC) bus, a two-wire Display Data Channel (DDC) bus that is essentially an I

C bus, a Hot Plug

Detect (HPD) signal, a 5V signal capable of delivering up to 50mA, and one reserved (RES) pin. Of these, the

differential data channels, I

C bus, and CEC are connected to the FPGA.

VGA

The Anvyl provides a 12bit VGA interface which allows up to 4096 colors displayed on a standard VGA Monitor.

The five standard VGA signals Red, Green, Blue, Horizontal Sync (HS), and Vertical Sync (VS) are routed directly

from the FPGA to the VGA connector. There are four signals routed from the FPGA for each of the standard VGA

color signals resulting in a video system that can produce 4,096 colors. Each of these signals has a series resistor

Other product and company names mentioned may be trademarks of their respective owners.

Page

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