EMBEDDED WRITE-BACK ENHANCED
IntelDX4™ PROCESSOR
s
Up to 100 MHz Operation
s
Integrated Floating-Point Unit
s
Speed-Multiplying Technology
s
32-Bit RISC Technology Core
s
16-Kbyte Write-Back Cache
s
3.3 V Core Operation with 5 V Tolerant
s
SL Technology
s
Data Bus Parity Generation and Checking
s
Boundary Scan (JTAG)
s
3.3-Volt Processor, 75 MHz, 25 MHz CLK
I/O Buffers
s
Burst Bus Cycles
s
Dynamic Bus Sizing for 8- and 16-bit
Data Bus Devices
— 208-Lead Shrink Quad Flat Pack (SQFP)
s
3.3-Volt Processor, 100 MHz, 33 MHz CLK
— 208-Lead Shrink Quad Flat Pack (SQFP)
— 168-Pin Pin Grid Array (PGA)
s
Binary Compatible with Large Software
Base
64-Bit Interunit Transfer Bus
32-Bit Data Bus
32-Bit Data Bus
Linear Address
CLKMUL
Core
Clock
32
PCD
PWT
Clock
Multiplier
CLK
Barrel
Shifter
Base/
Index
Bus
32
Segmentation
Unit
2
Bus Interface
Cache Unit
32
A31-A2 BE3#- BE0#
Paging
Unit
20
Register
File
Descriptor
Registers
Address
Drivers
Write Buffers
4 x 32
D31-D0
Physical
Address
ALU
Limit and
Attribute PLA
Translation
Lookaside
Buffer
16 Kbyte
Cache
32
32
Data Bus
Transceivers
Bus Control
ADS# W/R# D/C# M/IO# PCD
PWT RDY# LOCK# PLOCK#
BOFF# A20M# BREQ HOLD
HLDA RESET SRESET INTR
NMI SMI# SMIACT# FERR#
IGNNE# STPCLK#
Displacement Bus
32
128
Request
Sequencer
Prefetcher
Micro-
Instruction
32-Byte Code
Queue
2 x 16 Bytes
Burst Bus
Control
BRDY# BLAST#
Floating
Point Unit
Control &
Protection
Test Unit
Code
Stream
Bus Size
Control
BS16# BS8#
Instruction
Decode
24
Cache
Control
KEN# FLUSH# AHOLD EADS#
CACHE# HITM# INV WB/WT#
Floating
Point
Register File
Control
ROM
Decoded
Instruction
Path
Parity
Generation
and Control
Boundary
Scan
Control
PCHK# DP3-DP0
TCK TMS TDI TDO
A3232-01
Figure 1. Embedded Write-Back Enhanced IntelDX4™ Processor Block Diagram
© INTEL CORPORATION,
2004
August 2004
Order Number:
272771-003
Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or
"undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them.
The Embedded Write-Back Enhanced IntelDX4™ processor may contain design defects or errors known as
errata which may cause the product to deviate from published specifications. Current characterized errata are
available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your
product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 1997,
2004
*Third-party brands and names are the property of their respective owners.
Contents
EMBEDDED WRITE-BACK ENHANCED
IntelDX4™ PROCESSOR
1.0 INTRODUCTION ........................................................................................................................................ 1
1.1 Features ............................................................................................................................................. 1
1.2 Family Members ........................................................................................................... ...................... 2
2.0 HOW TO USE THIS DOCUMENT ................................................................................................. ............ 3
3.0 PIN DESCRIPTIONS ......................................................................................................... ........................ 3
3.1 Pin Assignments ................................................................................................................................. 3
3.2 Pin Quick Reference ......................................................................................................................... 16
4.0 ARCHITECTURAL AND FUNCTIONAL OVERVIEW ............................................................................. 26
4.1 CPUID Instruction ............................................................................................................................. 26
4.1.1 Operation of the CPUID Instruction ....................................................................................... 26
4.2 Identification After Reset .................................................................................................................. 28
4.3 Boundary Scan (JTAG) .................................................................................................................... 28
4.3.1 Device Identification ............................................................................................................... 28
4.3.2 Boundary Scan Register Bits and Bit Order ........................................................................... 29
5.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 30
5.1 Maximum Ratings ............................................................................................................................. 30
5.2 DC Specifications ............................................................................................................................. 30
5.3 AC Specifications ............................................................................................................................. 33
5.4 Capacitive Derating Curves .............................................................................................................. 40
6.0 MECHANICAL DATA .............................................................................................................................. 42
6.1 Package Dimensions ........................................................................................................................ 42
6.2 Package Thermal Specifications ...................................................................................................... 44
FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Embedded Write-Back Enhanced IntelDX4™ Processor Block Diagram ................................... i
Package Diagram for 208-Lead SQFP Embedded Write-Back Enhanced
IntelDX4™ Processor ................................................................................................................ 4
Package Diagram for 168-Pin PGA Embedded Write-Back Enhanced
IntelDX4™ Processor .............................................................................................................. 10
CLK Waveform ........................................................................................................................ 36
Input Setup and Hold Timing ................................................................................................... 36
Input Setup and Hold Timing ................................................................................................... 37
PCHK# Valid Delay Timing ...................................................................................................... 37
Output Valid Delay Timing ....................................................................................................... 38
Maximum Float Delay Timing .................................................................................................. 38
TCK Waveform ........................................................................................................................ 39
Test Signal Timing Diagram .................................................................................................... 39
iii
Contents
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a Low-to-High Transition ..................................................................................................... 40
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a High-to-Low Transition ..................................................................................................... 40
Typical Loading Delay versus Load Capacitance in Mixed Voltage System ........................... 41
208-Lead SQFP Package Dimensions .................................................................................... 42
Principal Dimensions and Data for 168-Pin Grid Array Package ............................................. 43
The Embedded Write-Back Enhanced IntelDX4™ Processor Family ....................................... 2
Pinout Differences for 208-Lead SQFP Package ...................................................................... 5
Pin Assignment for 208-Lead SQFP Package ........................................................................... 6
Pin Cross Reference for 208-Lead SQFP Package ................................................................... 8
Pinout Differences for 168-Pin PGA Package ......................................................................... 11
Pin Assignment for 168-Pin PGA Package .............................................................................. 12
Pin Cross Reference for 168-Pin PGA Package ...................................................................... 14
Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions ............................. 16
Output Pins .............................................................................................................................. 24
Input/Output Pins ..................................................................................................................... 24
Test Pins .................................................................................................................................. 25
Input Pins ................................................................................................................................. 25
CPUID Instruction Description ................................................................................................. 26
Boundary Scan Component Identification Code (Write-Through/Standard Bus Mode) ........... 28
Boundary Scan Component Identification Code (Write-Back/Enhanced Bus Mode) ............... 29
Absolute Maximum Ratings ..................................................................................................... 30
Operating Supply Voltages ...................................................................................................... 30
DC Specifications ..................................................................................................................... 31
I
CC
Values ................................................................................................................................ 32
AC Characteristics ................................................................................................................... 33
AC Specifications for the Test Access Port ............................................................................. 35
168-Pin Ceramic PGA Package Dimensions ........................................................................... 43
Ceramic PGA Package Dimension Symbols ........................................................................... 44
Thermal Resistance,
θ
JA
(°C/W) ............................................................................................. 45
Thermal Resistance,
θ
JC
(°C/W) ............................................................................................. 45
Maximum T
ambient
, T
A
max (°C) ............................................................................................... 45
iv
Embedded Write-Back Enhanced IntelDX4™ Processor
1.0
INTRODUCTION
1.1
Features
The embedded Write-Back Enhanced IntelDX4™
processor provides high performance to 32-bit,
embedded applications. Designed for applications
that need a floating-point unit, the processor is ideal
for embedded designs running DOS*, Microsoft
Windows*, OS/2*, or UNIX* applications written for
the Intel architecture. Projects can be completed
quickly using the wide range of software tools,
utilities, assemblers and compilers that are available
for desktop computer systems. Also, developers can
find advantages in using existing chipsets and
peripheral components in their embedded designs.
The Embedded Write-Back Enhanced IntelDX4
processor is binary compatible with the Intel386™
and earlier Intel processors. Compared with the
Intel386 processor, it provides faster execution of
many commonly-used instructions. It also provides
the benefits of an integrated, 16-Kbyte, write-back
cache for code and data. Its data bus can operate in
burst mode which provides up to 106-Mbyte-per-
second transfers for cache-line fills and instruction
prefetches.
Intel’s SL technology is incorporated in the
Embedded
Write-Back
Enhanced
IntelDX4
processor. Utilizing Intel’s System Management
Mode (SMM) enables designers to develop energy-
efficient systems.
Two component packages are available:
• 168-pin Pin Grid Array (PGA)
• 208-lead Shrink Quad Flat Pack (SQFP)
The processor operates at either two or three times
the external bus frequency. At two times the external
bus frequency the processor operates up to 66 MHz,
(33-MHz CLK). At three times the external bus
frequency the processor operates up to 100 MHz
(33-MHz CLK).
The Embedded Write-Back Enhanced IntelDX4
processor offers these features:
•
32-bit RISC-Technology Core
— The Embedded
Write-Back Enhanced IntelDX4 processor
performs a complete set of arithmetic and logical
operations on 8-, 16-, and 32-bit data types using
a full-width ALU and eight general purpose
registers.
•
Single Cycle Execution
— Many instructions
execute in a single clock cycle.
•
Instruction Pipelining
— Overlapped instruction
fetching, decoding, address translation and
execution.
•
On-Chip Floating-Point Unit
— Intel486™
processors support the 32-, 64-, and 80-bit formats
specified in IEEE standard 754. The unit is binary
compatible with the 8087, Intel287™, Intel387™
coprocessors, and Intel OverDrive
®
processor.
•
On-Chip Cache with Cache Consistency
Support
— A 16-Kbyte internal cache is used for
both data and instructions. It is configurable to be
write-back or write-through on a line-by-line basis.
The internal cache implements a modified MESI
protocol, which is applicable to uniprocessor
systems. Cache hits provide zero wait-state
access times for data within the cache. Bus activity
is tracked to detect alterations in the memory
represented by the internal cache. The internal
cache can be invalidated or flushed so that an
external cache controller can maintain cache
consistency.
•
External Cache Control
— Write-back and flush
controls for an external cache are provided so the
processor can maintain cache consistency.
•
On-Chip Memory Management Unit
— Address
management and memory space protection
mechanisms maintain the integrity of memory in a
multitasking and virtual memory environment. Both
memory segmentation and paging are supported.
•
Burst Cycles
— Burst transfers allow a new
double-word to be read from memory on each bus
clock cycle. This capability is especially useful for
instruction prefetch and for filling the internal
cache. Data written from the processor to memory
can also be burst transfers.
•
Write Buffers
— The processor contains four
write buffers to enhance the performance of
consecutive writes to memory. The processor can
continue internal operations after a write to these
buffers, without waiting for the write to be
completed on the external bus.
1
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