Crystal oscillator
Epson Toyocom
Product Number (please contact us)
CRYSTAL OSCILLATOR
Low Profile / LOW-JITTER SPXO
X1G0029x1xxxx00
SG - 210 S*D
Frequency
range
:
Supply
voltage
:
Current
consumption
:
:
Function
:
External
dimensions
:
50.000 MHz to 80.000 MHz
1.8 V / 2.5 V / 3.3 V
7.0 mA Max.
(SDD: 2.5 V No load condition 80 MHz)
Standby(
ST
)
2.5 × 2.0 × 0.8 mm
Actual size
Specifications (characteristics)
Item
Output frequency range
Supply voltage
Storage temperature
Operating temperature
Frequency tolerance
Current consumption
Stand-by current
Symmetry
Output voltage
Output load condition
(CMOS)
Input voltage
Rise time / Fall time
Start-up time
Jitter *1
Phase Jitter
Frequency aging
Symbol
f
0
V
CC
T_stg
T_use
f_tol
I
CC
I_std
SYM
V
OH
V
OL
L_CMOS
V
IH
V
IL
Specifications
SG-210SED
SG-210SDD
SG-210SCD
50.000 MHz to 80.000 MHz
1.8 V Typ.
2.5 V Typ.
3.3 V Typ.
-40
C
to +125 °C
-40
C
to +85 °C
B:
50
× 10
-6
, C:
100
× 10
-6
L:
50
× 10
-6
, M:
100
× 10
-6
6.0 mA Max.
7.0 mA Max.
8.0 mA Max.
10.0 µA Max.
45 % to 55 %
V
CC
-0.4 V Min.
0.4 V Max.
30 pF Max.
70 % V
CC
Min.
30 % V
CC
Max.
4 ns Max.
2 ms Max.
0.1 ps Typ.
3.2 ps Typ.
30 ps Typ.
0.1 ps Typ.
2.7 ps Typ.
25 ps Typ.
1.0 ps Max.
3
× 10 / year Max..
-6
Conditions / Remarks
1.6 V to 2.2 V
2.2 V to 3.0 V
2.7 V to 3.6 V
Store as bare product.
-20
C
to +70
C
-40
C
to +85
C
No load condition
ST
=GND
50 % V
CC
level,L_CMOS
30 pF
I
OH
=-8 mA(SCD,SDD), -4 mA(SED)
I
OL
= 8 mA(SCD,SDD), 4 mA(SED)
ST
terminal
t
r
/
t
f
t
_
str
t
DJ
t
RJ
t
RMS
t
PJ
f_aging
10
× 10
-6
/ 10 years Max.
20 % V
CC
to 80 % V
CC
level,
L_CMOS
30 pF
t=0 at 90 % V
CC
Deterministic Jitter
Random Jitter
L_CMOS
15 pF
Peak to Peak
Offset frequency:
12 kHz to 20 MHz
+25 °C, First year,
V
CC
= 1.8 V, 2.5 V, 3.3 V
+25 °C, 10 years,
V
CC
= 1.8 V, 2.5 V, 3.3 V
*1
Based on DTS-2075 Digital timing system made from WAVECREST with jitter analysis software VISI6.
External dimensions
2.50.15
#4
#3
#3
(Unit:mm)
Footprint (Recommended)
C
(ex. 0.01 µF)
(Unit:mm)
#4
Resist
0.7 0.6
50.00B
B631A
#1
#2
2.00.15
#4
1.1
#3
#2
0.9
0.8
#1
0.80.1
Pin map
Pin
1
2
3
4
Connection
ST
GND
OUT
V
CC
1.3
#1
#2
1.7
To maintain stable operation, provide a 0.01uF to
0.1uF by-pass capacitor at a location as near as
possible to the power source terminal of the crystal
product (between Vcc - GND).
Note.
ST
pin = HIGH or "open" : Specified frequency output.
ST
pin = LOW : Output is high impedance, oscillation stops.
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0.9
PCB Design
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