Si2163
DVB-C Demodulator
Description
The Si2163 is a compact, standalone DVB-C digital TV
demodulator ideally matching Silicon Labs’ Si2170/1/2 new
hybrid silicon tuner product family. The analog front-end
consists of two ADCs with wide dynamic range (12-bit) to
allow operation with standard IF (~36 MHz), Low-IF, or
Zero-IF inputs. This enables the use of the Si2163 with any
TV tuner, either metal can or silicon tuner based. The
Si2163 supports ITU J.83 annex A/C and DVB-C (EN 300
429) and accepts symbol rates from 1 to 7.2 MSymbol/s.
The Si2163 includes a user-configurable 31-tap equalizer
for optimum reception even in case of difficult network
conditions, such as long echoes.
Serial or parallel master MPEG TS output modes are
supported. Furthermore, a TS slave parallel mode is
available via a GPIF port and provides glue less interface
to Silicon Labs' MCU devices with embedded USB
interface. The user can optionally program a 32-PID
hardware filter to reduce the output TS bit rate (or add
more TS security for Pay-TV channels).
The Si2163 supports ultra-fast channel scanning
operations for VHF/UHF digital cable channels, thanks to
an embedded DSP. For supported tuners, the complete
algorithm for fast channel scan,
QuickScan,
is provided as
a downloadable patch file.
QuickScan
runs on the
embedded DSP to limit the host CPU / MPEG decoder
software burden.
An internal I
2
C pass-through logic switch acts as an I
2
C
repeater and provides a "quiet" I
2
C bus to the RF front end.
A maximum of six general-purpose inputs/outputs are
available; three GPIOs also feature
/
and interrupt
output capabilities.
Best-in-class demodulation performance is achieved while
still maintaining very low-power operation. The Si2163
guarantees a low-cost system implementation due to its
minimal BOM and very small package footprint. The
Si2163 remains pin-to-pin compatible with Si2161 (DVB-T)
and Si2165 (DVB-T/C) devices.
1.2, 3.3V
RF_AGC
IF_AGC
RSSI
ADC_IP
ADC_IN
ADC_QP
ADC_QN
4 MHz
or
TUN_SDA
TUN_SCL
Xtal: 16,20,
24,27 MHz
I
2
C
SWITCH
OSC
& PLL
µP
I/F
I
2
C
I/F
HOST_SDA
HOST_SCL
Features
-
ITU J.83 Annex A/C and DVB-C (EN 300 429) compliant
-
NorDig Unified 2.0 and C-Book compliant
-
Suitable for low power design: 120 mW (typical, 36 MHz
IF normal sampling mode)
-
Dual 12-bit ADCs: accept 1
st
IF, low IF, or zero-IF inputs.
-
Symbol rate from 1 to 7.2 MBaud
-
Independent AGC controls (for IF & RF), plus RSSI
-
-
-
-
measurement
On-chip ACI filtering: fixed 8 MHz SAW filter even for
low symbol rates
Ultra fast, DSP controlled, automatic UHF/VHF band
scanning (QuickScan)
Master TS output modes, parallel or serial (with tri-state
function)
Slave TS parallel output: external device polls data from
an embedded FIFO, providing a seamless interface to
any USB controller.
On-chip PID filtering to reduce TS output bit rate
Up to six GPIOs
-
-
-
Two 5 V tolerant I
2
C control buses (host-side,
tuner-side) with on-chip I
2
C logic switch.
-
4, 16, 20, 24, or 27 MHz clock/crystal reference
-
3.3 and 1.2 V power supplies only
-
Very compact QFN-36, 5 x 6 mm, RoHS compliant
package
Applications
-
Digital cable STB, NIM, and iDTV set
-
Cable enabled Personal Video Recorder
(DVD or HDD-based)
-
Digital cable PC-TV card or peripheral
RESETB
Dual
AGC
8-bit
ADC
12-bit
ADC
12-bit
ADC
Si2163
DSP
CTRL
TS
I/F
GPIO
GPIO0..5
(Can or Silicon) TUNER
TS & GPIF INTERFACE
FRONT
END
DVB-C
DEMOD
EQUALI
ZER
FEC
PID
FILTER
8
Digital TV Demodulator
Copyright © 2009 by Silicon Laboratories
MPEG ASSP
TS_SYNC
TS_VAL
TS_ERR
TS_CLK
TS_DATA
7.22.09
Si2163
DVB-C Demodulator
Selected Electrical Specifications
Parameter
General
Ambient Temperature
Power-up Time
I
2
C Speed (Host side)
Input Clock or Supported Xtal Frequency
VDD_VCORE Supply
VDD_VIO Supply**
VDD_VADC
VDDH_VANA
Input ADC (2 x 12-bits)
Input Differential Voltage Range
IF Oversampling Mode Clock
IF Sub-sampling Mode Clock
ZIF Mode Sampling Clock
System Clock
TS Output Rates
Serial Mode Clock
Power Consumption
DVB-C, 6.9 MBaud, 256 QAM (adc_clk @ 56 MHz),
Parallel TS
Total Stand-by Power Consumption
—
—
120
13
—
—
mW
mW
—
—
65
MHz
—
37
18.5
18.5
—
1
48
27
48
—
—
60
32.5
60
85
Vpp
MHz
MHz
MHz
MHz
0
—
<1
—
1.14
1.62
1.14
3.00
25
—
—
4*/16/20/24/27
1.2
1.80 to 3.30
1.2
3.30
85
10
400
—
1.26
3.60
1.26
3.60
°C
ms
kHz
MHz
V
V
V
V
Min
Typ
Max
Unit
*Note:
Clock only.
**Note:
5 V tolerant I
2
C bus requires VDD_VIO supply set @ 3.3 V.
Pin Assignments
TS_ERR/GPIO_2
VDDH_VANA
5 x 6 mm SLP QFN-36 Package Information
VDD_VCORE
RESETB
XTAL_O
XTAL_I
TS_DATA[7]
9
TS_CLK/GPIF_CTL
VDD_VADC
ADDR
28 27 26 25 24 23 22 21 20 19
ADC_IP 29
ADC_IN 30
ADC_QP 31
ADC_QN 32
SDA_MAST 33
SCL_MAST 34
RSSI_ADC/CLK_OUT 35
GPIO_0 36
1
GND
2
AGC_IF
3
AGC_RF
4
SCL_HOST
5
SDA_HOST
6
VDD_VCORE
7
TS_VAL/GPIF_CLK
8
TS_SYNC/GPIF_RDY
10
GND
GND
18 TS_DATA[6]
17 TS_DATA[5]
16 TS_DATA[4]/GPIO_5
15 VDD_VIO
14 TS_DATA[3]/GPIO_4
13 TS_DATA[2]/GPIO_3
12 TS_DATA[1]/GPIO_1
11 TS_DATA[0]/TS_SER
Digital TV Demodulator
Copyright © 2009 by Silicon Laboratories
GND
7.22.09
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
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