XC5VSX50T-1FFG665I datasheet, PDF

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XC5VSX50T-1FFG665I: DescriptionIC fpga 360 I/O 665fcbga; CategoryProgrammable logic devices Programmable logic; File Size2MB，166 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/; Environmental Compliance

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IC fpga 360 I/O 665fcbga

XC5VSX50T-1FFG665I Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	XILINX
Parts packaging code	BGA
package instruction	BGA, BGA665,26X26,40
Contacts	665
Reach Compliance Code	_compli
ECCN code	3A991.D
Combined latency of CLB-Max	0.9 ns
JESD-30 code	S-PBGA-B665
JESD-609 code	e1
length	27 mm
Humidity sensitivity level	4
Configurable number of logic blocks	4080
Number of entries	360
Number of logical units	52224
Output times	360
Number of terminals	665
Maximum operating temperature	100 °C
Minimum operating temperature	-40 °C
organize	4080 CLBS
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA665,26X26,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	250
power supply	1,2.5 V
Programmable logic type	FPGA
Certification status	Not Qualified
Maximum seat height	2.9 mm
Maximum supply voltage	1.05 V
Minimum supply voltage	0.95 V
Nominal supply voltage	1 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	27 mm
Base Number Matches	1

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Virtex-5 FPGA

Configuration User

Guide

UG191 (v3.12) May 8, 2017

Disclaimer

The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum

extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL

WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF

MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether

in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising

under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or

consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action

brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.

Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product

specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are

subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at

www.xilinx.com/legal.htm#tos;

IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx

products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and

liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at

www.xilinx.com/legal.htm#tos.

herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document.

Date

04/14/2006

05/12/2006

Version

1.0

1.1

Revision

Initial Xilinx release.

Minor typographical edits to entire document to improve clarity.

Chapter 1: Revised

Table 1-1, Table 1-2, Table 1-9, Table 1-11.

Chapter 2: Clarified bit-swapping (Byte Swap rule) throughout. Updated

“Page Mode

Support,” page 71.

Chapter 8: Added new section called

“MultiBoot Bitstream Spacing,” page 155.

Chapter 9: Added

“Post_CRC Constraints”

section.

Virtex-5 FPGA Configuration Guide

www.xilinx.com

UG191 (v3.12) May 8, 2017

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