™
Le75183
Line Card Access Switch
VE750 Series
Data Sheet
Features
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Small size/surface-mount packaging
Monolithic IC reliability
Low impulse noise
Make-before-break, break-before-make operation
Clean, bounce-free switching
Low, matched ON-resistance
Built-in current limiting, thermal shutdown and
SLIC protection
5 V only operation, very low power consumption
Battery monitor, all OFF state upon loss of battery
No EMI
Latched logic level inputs, no drive circuitry
Only one external protector required
TTL logic control compatible
Default power up state
Device
Le75183ADSC
Le75183BDSC
Le75183CDSC
Le75183AFQC
Le75183BFQC
LE75183CFQC
LE75183AFSC
Le75183BFSC
Le75183CZFSC
1. The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of electrical
equipment.
2. For delivery using a tape and reel packing system, add a "T" suffix to
the OPN (Ordering Part Number) when placing an order.
28 Pin SOIC (GULL)
Tube
32 Pin QFN
Tray
20 Pin SOIC (GULL)
Tube
Package Type
Packing
2
Document ID#:081126
Version
6
April 2011
Ordering Information
Applications
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Central office
DLC
PBX
DAML
HFC/FITL
Description
The VoiceEdge™ family VE750 series of Line Card
Access Switches (LCAS), which includes the Le75181,
Le75282 and Le75183 devices, is a family of
monolithic solid-state switches that is designed to
provide both power ringing access and test access on
the analog line card. These devices, while not a pin-
for-pin
replacement
for
the
traditional
electromechanical relay (EMR) solution, provide the
equivalent switching functionality. The VE750 series of
LCAS is meant as a solid-state alternative to the
EMRs.
The Le75183A/B/C devices are pin-for-pin compatible
with Zarlink’s L7583A/B/C devices.
Zarlink also offers a range of compatible SLIC devices
and codec/filters that can be used with the VE750
series LCAS for complete line card solutions that can
be used worldwide in analog line card applications.
Related Literature
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081123 Le75282 Dual Intelligent Line Card
Access Switch Data Sheet
081105 Le75181 Ringing Access Switch Data
Sheet
080754 Le58QL061/063 QLSLAC Data Sheet
080676 Le5711 Dual SLIC Data Sheet
081047 Le5712 Dual SLIC Data Sheet
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2007-2010, Zarlink Semiconductor Inc. All Rights Reserved.
Le75183
Table of Contents
Data Sheet
1.0 Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.0 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.0 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.0 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.0 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 Environmental Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 Electrical Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.3 Handling Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.1 Summary of Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.2 Supply Currents and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.0 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.1 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
8.0 Zero Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9.0 Switching Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10.0 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
11.0 Loss of Battery Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
12.0 Impulse Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
13.0 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
13.1 Integrated SLIC Device Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
13.1.1 Diode Bridge/SCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
13.1.2 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
13.1.3 Temperature Shutdown Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
13.1.4 External Secondary Protector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
14.0 Typical Performance Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
15.0 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
16.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
16.1 28-Pin, Plastic SOIC (GULL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
16.2 20-Pin, Plastic SOIC (GULL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
16.3 32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
17.0 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
17.1 Revision A1 to B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
17.2 Revision B1 to C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
17.3 Revision C1 to C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
17.4 Revision C2 to Ver 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
17.5 Revision Ver 5 to Ver 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Zarlink Semiconductor Inc.
Le75183
List of Figures
Data Sheet
Figure 1 - Le75183A/C Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2 - Le75183B Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3 - Protection Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 4 - Switches 3, 7, 9, and 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5 - Switch 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6 - Switches 1, 2, and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7 - Switches 6, 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8 - Typical LCAS Application, A/C Versions, Idle or Talk State Shown . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Zarlink Semiconductor Inc.
Le75183
1.0
Product Description
Data Sheet
The Le75183A/B/C Line Card Access Switch is a monolithic solid-state device providing the equivalent switching
functionality of three 2 form C switches. The Le75183 is designed to provide power ringing access, line test access
(test out), and SLIC test access (test in) to tip and ring in central office, digital loop carrier, private branch exchange,
digitally added main line, and hybrid fiber coax/fiber-in-the-loop analog line card applications. An additional pair of
solid-state contacts are also available to provide access for testing of the ringing generator.
The Le75183A/B has seven states: the idle talk state (line break switches closed, all other switches open), the
power ringing state (ringing access switches closed, all other switches open), loop access (test out) state (loop
access (test out) switches closed, all other switches open), SLIC test state (test in switches closed, all other
switches open), simultaneous loop and SLIC access state (loop and test in switches closed, all others open),
ringing generator test state (ring test switches closed, all others open), and an all OFF state. The seven states in
the Le75183A/B are also in the Le75183C, with an additional simultaneous test-out and ring-test state, making the
Le75183C appropriate for digital loop carrier and other Telcordia TR-57 applications.
The Le75183 offers break-before-make or make-before-break switching, with simple logic level input control.
Because of the solid-state construction, voltage transients generated when switching into an inductive ringing lead
during ring cadence or ring trip are minimized, possibly eliminating the need for external zero cross switching
circuitry. State control is via logic level inputs, so no additional driver circuitry is required.
The line break switch is a linear switch that has exceptionally low ON-resistance and an excellent ON-resistance
matching characteristic. The ringing access switch has a breakdown voltage rating >480 V which is sufficiently high,
with proper protection, to prevent breakdown in the presence of a transient fault condition (i.e., passing the
transient on to the ringing generator).
Incorporated into the Le75183A and Le75183C is a diode bridge/SCR clamping circuit, current-limiting circuitry, and
a thermal shutdown mechanism to provide protection to the SLIC device and subsequent circuitry during fault
conditions. This is shown in block diagram as version A/C. Positive and negative lightning is reduced by the
current-limiting circuitry and steered to ground via diodes and the integrated SCR. Power cross is also reduced by
the current-limiting and thermal shutdown circuits.
The Le75183B version provides only an integrated diode bridge along with current limiting and thermal shutdown
(see block diagram for version B). This will cause positive faults to be directed to ground and negative faults to
battery. In either polarity, faults are reduced by the current-limit and/or thermal shutdown mechanisms.
To protect the Le75183 from an overvoltage fault condition, use of a secondary protector is required. The
secondary protector must limit the voltage seen at the tip/ring terminals to prevent the breakdown voltage of the
switches from being exceeded. To minimize stress on the solid-state contacts, use of a foldback- or crowbar- type
secondary protector is recommended. With proper choice of secondary protection, a line card using the Le75183
will meet all relevant ITU-T, LSSGR, FCC, or UL* protection requirements.
The Le75183 operates off of a 5 V supply only. This gives the device extremely low idle and active power
dissipation and allows use with virtually any range of battery voltage. This makes the Le75183 especially
appropriate for remote power applications such as DAML or FOC/FITL or other Telcordia TA 909 applications
where power dissipation is particularly critical.
A battery voltage is also used by the Le75183, only as a reference for the integrated protection circuit. The Le75183
will enter an all OFF state upon loss of battery.
During power ringing, to turn on and maintain the ON state, the ring access switch and ring test switch will draw a
nominal 2 mA from the ring generator.
The default power up state of Le75183 is in all OFF state, unless otherwise being overwritten by external controls.
The Le75183 device is packaged in a 20-pin, plastic SOIC (GULL) (Le75183ADSC/BDSC/CDSC), a 32-pin QFN
(Le75183AFQC/BFQC/CFQC), and a 28-pin, plastic SOIC (GULL) (Le75183AFSC/BFSC/CZFSC). The 28-pin
package is available to support existing designs. For new designs, it may be advantageous to use the other two
smaller size packages.
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Zarlink Semiconductor Inc.
Le75183
2.0
Block Diagrams
Le75183A/C
FGND
SCR
& Trip
Circuit
VBAT
Data Sheet
SW1
SW2
TTESTin
TBAT
TLINE
TRINGING
SW7
SW8
SW10
SW3
SW5
SW4
SW6
RTESTin
RBAT
RLINE
RRINGING
TTESTout
SW9
RTESTout
LATCH
VDD
TSD
DGND
Control
Logic
INTESTin
INRING
INTESTout
Figure 1 - Le75183A/C Block Diagram
Le75183B
FGND
VBAT
TTESTin
TBAT
TLINE
TRINGING
SW1
SW2
RTESTin
RBAT
SW3
SW5
SW4
SW6
RLINE
RRINGING
SW7
SW8
TTESTout
SW9
SW10
RTESTout
LATCH
VDD
TSD
DGND
Control
Logic
INTESTin
INRING
INTESTout
Figure 2 - Le75183B Block Diagram
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Zarlink Semiconductor Inc.