a
FEATURES
Supports DOCSIS Standard for Reverse Path
Transmission
Gain Programmable in 6.02 dB Steps over a 48.16 dB
Range
Low Distortion at 60 dBmV Output
–63 dBc SFDR at 21 MHz
–57 dBc SFDR at 42 MHz
Output Noise Level
–47 dBmV in 160 kHz
Maintains 75 Output Impedance
Transmit Enable and Transmit Disable Modes
Upper Bandwidth: 160 MHz (Full Gain Range)
5 V Supply Operation
Supports SPI Interfaces
APPLICATIONS
Gain-Programmable Line Driver
DOCSIS High-Speed Data Modems
Interactive Cable Set-Top Boxes
PC Plug-in Cable Modems
General-Purpose Digitally Controlled Variable Gain Block
5 V CATV Line Driver Coarse Step
Output Power Control
AD8327
FUNCTIONAL BLOCK DIAGRAM
V
CC
(5 PINS)
BYP
R1
AD8327
V
IN+
V
IN–
DIFF OR
SINGLE
INPUT
AMP
VERNIER
ATTENUATION
CORE
POWER
AMP
Z
OUT
= 75
V
OUT
8
TE
R2
DECODE
8
Z
IN
(SINGLE) = 800
Z
IN
(DIFF) = 1.6k
DATA LATCH
8
POWER-DOWN
LOGIC
CXR
SHIFT
REGISTER
LE
DATEN
DATA
CLK
GND (5 PINS)
TXEN
SLEEP
GENERAL DESCRIPTION
–50
DISTORTION – dBc
The AD8327 is a low-cost, digitally controlled, variable gain
amplifier optimized for coaxial line driving applications such as
cable modems that are designed to the MCNS-DOCSIS
upstream standard. An 8-bit serial word determines the desired
output gain over a 48.16 dB range resulting in gain changes of
6.02 dB/major carry.
SO
V
OUT
= 60dBmV @ MAX GAIN
–55
HD3
–60
HD2
–65
B
The AD8327 comprises a digitally controlled variable attenuator
of 0 dB to –48.16 dB, which is preceded by a low noise, fixed
gain buffer and followed by a low distortion, high power amplifier.
The AD8327 accepts a differential or single-ended input
signal. The output is specified for driving a 75
Ω
load, such
as coaxial cable.
Distortion performance of –63 dBc is achieved with an output
level up to 60 dBmV at 21 MHz bandwidth. A key performance
and cost advantage of the AD8327 results from the ability to
maintain a constant 75
Ω
output impedance during Transmit
Enable and Transmit Disable conditions. In addition, this
device has a sleep mode function that reduces the quiescent
current to 5 mA.
The AD8327 is packaged in a low-cost 20-lead TSSOP, operates
from a single 5 V supply, and has an operational temperature
range of –40°C to +85°C.
–70
–75
5
15
25
35
45
55
FUNDAMENTAL FREQUENCY – MHz
65
O
Figure 1. Harmonic Distortion vs. Frequency
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD8327–SPECIFICATIONS
(T = 25 C, V = 5 V, R = 75
A
S
L
, V
IN(DIFFERENTIAL)
= 30 dBmV)
Min
Typ
30
13.2
800
1600
2
47.16
29
–19.16
48.16
30
–18.16
6.02
Max
Unit
dBmV
dB
Ω
Ω
pF
49.16 dB
31
dB
–17.16 dB
dB/Major
Carry
MHz
dB
dB
dBmV in
160 kHz
dBmV in
160 kHz
dBmV in
160 kHz
dBm
Ω
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
ns
ns
dBc
Parameter
INPUT CHARACTERISTICS
Specified AC Voltage
Noise Figure
Input Resistance
Input Capacitance
GAIN CONTROL INTERFACE
Gain Range
Maximum Gain
Minimum Gain
Gain Scaling Factor
OUTPUT CHARACTERISTICS
Bandwidth (–3 dB)
Bandwidth Roll-Off
Bandwidth Peaking
Output Noise Spectral Density
Conditions
P
OUT
= 60 dBmV, Max Gain
Max Gain, f = 10 MHz
Single-Ended Input
Differential Input
Gain Code = 10000000 (128 Decimal)
Gain Code = 00000000 (0 Decimal)
Min Gain, f = 10 MHz
1 dB Compression Point
Differential Output Impedance
OVERALL PERFORMANCE
Second Order Harmonic Distortion
Third Order Harmonic Distortion
Adjacent Channel Power
LE
4.75
75
40
10
3
–40
–2–
Transmit Disable Mode (TXEN = 0),
f = 10 MHz
Max Gain, f = 10 MHz
Transmit Enable (TXEN = 1) and
Transmit Disable Mode (TXEN = 0)
SO
Ramp Setting
2
POWER SUPPLY
Operating Range
Quiescent Current
O
POWER CONTROL
Transmit Enable Settling Time (T
ON
)
1
Transmit Disable Settling Time (T
OFF
)
1
Transmit Enable Settling Time (T
ON
)
2
Transmit Disable Settling Time (T
OFF
)
2
Between Burst Transients
2
B
Gain Linearity Error
Output Settling
Due to Gain Change (T
GS
)
Due to Input Change
Isolation in Transmit Disable Mode
f = 21 MHz, V
OUT
= 60 dBmV @ Max Gain
f = 42 MHz, V
OUT
= 60 dBmV @ Max Gain
f = 65 MHz, V
OUT
= 60 dBmV @ Max Gain
f = 21 MHz, V
OUT
= 60 dBmV @ Max Gain
f = 42 MHz, V
OUT
= 60 dBmV @ Max Gain
f = 65 MHz, V
OUT
= 60 dBmV @ Max Gain
Adjacent Channel Width = Transmit Channel
Width = 160 K
SYM/SEC
f = 10 MHz, Code to Code
Min to Max Gain
Max Gain, V
IN
= 30 dBmV
Max Gain, TXEN = 0 V, f = 42 MHz,
V
IN
= 30 dBmV
Max Gain, V
IN
= 0 V
Max Gain, V
IN
= 0 V
Max Gain, V
IN
= 0 V
Max Gain, V
IN
= 0 V
Equivalent Output = 31 dBmV
Equivalent Output = 60 dBmV
TE
–47
–66
14.8
75
±
20%
–63
–61
–54
–63
–57
–57
–62
±
0.25
60
30
–52
300
40
2
1.7
3
25
2
5
105
60
15
5
5.25
135
80
20
7
+85
All Gain Codes
f = 65 MHz
All Gain Codes
Max Gain, f = 10 MHz
160
0.4
0
–32
ns
ns
µs
µs
mV p-p
mV p-p
µs
V
mA
mA
mA
mA
°C
Transmit Enable Mode (TXEN = 1) @ Dec 128
Transmit Enable Mode (TXEN = 1) @ Dec 0
Transmit Disable Mode @ All Gain Codes
Sleep Mode @ All Gain Codes
OPERATING TEMPERATURE
RANGE
NOTES
1
For Transmit Enable or Transmit Disable transitions using a 0 pF capacitor (at CXR pin) to ground.
2
For Transmit Enable or Transmit Disable transitions using a 100 pF capacitor (at CXR pin) to ground.
Specifications subject to change without notice.
REV. 0
AD8327
LOGIC INPUTS (TTL/CMOS-Compatible Logic)
(DATEN, CLK, SDATA, TXEN,
SLEEP,
V
Parameter
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (V
INH
= 5 V) CLK, SDATA,
DATEN
Logic “0” Current (V
INL
= 0 V) CLK, SDATA,
DATEN
Logic “1” Current (V
INH
= 5 V) TXEN
Logic “0” Current (V
INL
= 0 V) TXEN
Logic “1” Current (V
INH
= 5 V)
SLEEP
Logic “0” Current (V
INL
= 0 V)
SLEEP
Min
2.1
0
0
–600
50
–250
50
–250
Typ
CC
= 5 V: Full Temperature Range)
Max
5.0
0.8
20
–100
190
–30
190
–30
Unit
V
V
nA
nA
µA
µA
µA
µA
TIMING REQUIREMENTS
Parameter
(Full Temperature Range, V
CC
= 5 V, t
R
= t
F
= 4 ns, f
CLK
= 8 MHz unless otherwise noted.)
t
DS
SDATA
VALID DATA WORD G1
MSB. . . .LSB
SO
t
C
t
WH
CLK
t
ES
DATEN
B
TXEN
LE
VALID DATA WORD G2
Clock Pulsewidth (t
WH
)
Clock Period (t
C
)
Setup Time SDATA vs. Clock (t
DS
)
Setup Time
DATEN
vs. Clock (t
ES
)
Hold Time SDATA vs. Clock (t
DH
)
Hold Time
DATEN
vs. Clock (t
EH
)
Input Rise and Fall Times, SDATA,
DATEN,
Clock (t
R
, t
F
)
TE
16.0
32.0
5.0
15.0
5.0
3.0
10
GAIN TRANSFER (G1)
GAIN TRANSFER (G2)
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
t
EH
8 CLOCK
CYCLES
t
OFF
t
GS
t
ON
O
REV. 0
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
Figure 2. Serial Interface Timing
VALID DATA BIT
SDATA MSB
MSB-1
MSB-2
t
DS
CLK
t
DH
Figure 3. SDATA Timing
–3–
AD8327
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
SDATA
CLK
TXEN
V
CC
GND
V
CC
CXR
GND
GND
1
2
3
4
5
20
19
18
Supply Voltage +V
S
Pins 4, 6, 11, 12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltages
Pins 17, 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
0.5 V
Pins 1, 2, 3, 19, 20 . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V
Internal Power Dissipation
TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 mW
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DATEN
SLEEP
V
IN–
V
IN+
16
V
CC
TOP VIEW
(Not to Scale)
15
GND
6
7
8
9
14
BYP
13
GND
12
11
AD8327
17
V
CC
V
CC
V
OUT 10
PIN FUNCTION DESCRIPTIONS
Pin No.
1
2
Mnemonic
SDATA
CLK
Description
18
19
20
V
IN–
SLEEP
DATEN
O
Model
AD8327ARU
AD8327ARU-REEL
AD8327-EVAL
B
SO
Temperature Range
–40°C to +85°C
–40°C to +85°C
–4–
3
4, 6, 11, 12, 16
5, 8, 9, 13, 15
7
10
14
17
TXEN
V
CC
GND
CXR
V
OUT
BYP
V
IN+
Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the
internal register with the MSB (Most Significant Bit) first.
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-
slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to
the slave. This requires the input serial data word to be valid at or before this clock transition.
Logic “0” disables transmission. Logic “1” enables transmission.
Common Positive External Supply Voltage. A 0.1
µF
capacitor must decouple each pin.
Common External Ground Reference
Transmit Enable/Disable Timing Capacitor. This pin is decoupled with a 100 pF capacitor to GND.
Output Signal
Internal Bypass. This pin must be externally ac-coupled (0.1
µF
capacitor).
Noninverting Input. DC-biased to approximately V
CC
/2. Should be ac-coupled with a 0.1
µF
capacitor.
Inverting Input. DC-biased to approximately V
CC
/2. Should be ac-coupled with a 0.1
µF
capacitor.
Low Power Sleep Mode. Logic 0 enables Sleep mode, where Z
OUT
goes to 200
Ω
and supply
current is reduced to 5 mA. Logic 1 enables normal operation.
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic
0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta-
neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch
(holds the previous gain state) and simultaneously enables the register for serial data load.
LE
ORDERING GUIDE
Package Description
20-Lead TSSOP
20-Lead TSSOP
Evaluation Board
*Thermal
Resistance measured on SEMI standard 4-layer board.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8327 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
TE
JA
Package Option
RU-20
RU-20
85°C/W*
85°C/W*
WARNING!
ESD SENSITIVE DEVICE
REV. 0
Typical Performance Characteristics–AD8327
0
+V
S
10 F
–10
–20
TXEN = 0
V
IN
= 30dBmV
0.1 F
0.1 F
V
IN–
V
IN
165
V
IN+
0.1 F BYP CXR
0.1 F
100pF
GND
V
CC
ISOLATION – dBc
75
–30
–40
–50
–60
–70
–80
MIN GAIN
–90
1
100
10
FREQUENCY – MHz
1000
MAX GAIN
AD8327
0.1 F
TPC 1. Basic Test Circuit
0.6
0.5
0.4
GAIN ERROR – dB
0.3
0.2
0.1
0
–0.1
f
= 65MHz
LE
20
10
GAIN – dB
f
= 42MHz
f
= 10MHz
f
= 5MHz
–0.2
–0.3
0
16
SO
112
128
TXEN = 0
TXEN = 1
32
48
64
80
96
GAIN CONTROL – Decimal Code
TE
40
30
128D
64D
32D
16D
08D
04D
02D
01D
00D
0
–10
–20
–30
1
10
100
FREQUENCY – MHz
TPC 4. Isolation in Transmit Disable Mode
vs. Frequency
1000
TPC 2. Gain Error vs. Gain Control
TPC 5. AC Response
160
155
150
145
90
85
80
TXEN = 0
O
B
IMPEDANCE –
+V
S
0.1 F
V
IN–
IMPEDANCE –
140
75
70
65
TXEN = 1
135
130
125
120
115
1
V
IN
165
V
IN+
0.1 F
AD8327
GND
OUT
0.1 F
75
60
55
10
FREQUENCY – MHz
100
1
10
FREQUENCY – MHz
100
TPC 3. Input Impedance vs. Frequency
TPC 6. Output Impedance vs. Frequency
REV. 0
–5–
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