CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
Electrical Specifications
Test Conditions: V
DD
= 3V, AVDD = 10V, OUT = 5V, R
SET
= 24.9kΩ; Unless Otherwise Specified.
Typicals are at T
A
= +25°C
SYMBOL
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
PARAMETER
DC CHARACTERISTICS
V
DD
Supply Range -- Operating
V
DD
Supply Range -- EEPROM
Programming
V
DD
Supply Current
AVDD Supply Range
V
DD
V
DD
I
DD
AVDD
(Note 4)
VDD range 2.6V to 3.6V
VDD range 2.25V to 3.6V
Full
Full
Full
Full
2.25
2.6
-
4.5
4.5
-
-
-
-
-
-
7
3.6
3.6
50
18
13
25
V
V
µA
V
V
µA
Bits
AVDD Supply Current
SET Voltage Resolution
SET Differential Nonlinearity
SET Zero-Scale Error
SET Full-Scale Error
SET Current
SET External Resistance
IAVDD
SET
VR
SET
DN
SET
ZSE
SET
FSE
ISET
SET
ER
(Note 2)
Full
Full
-
Monotonic Over-Temperature
Full
Full
Full
-
-
-
-
10
2.25
-
-
VSET + 0.5V
-
0.7*VDD
-
-
-
-
-
20
-
-
1:20
8
-
<10
-
-
0.22*VDD
±1
±2
±8
-
200
45
-
-
13
-
-
0.3*VDD
-
LSB
LSB
LSB
µA
kΩ
kΩ
V/V
µs
V
mV
V
V
V
Through R
SET
(Note 5)
To GND, AVDD = 20V
To GND, AVDD = 4.5V
Full
Full
Full
Full
Full
Full
AVDD to SET Voltage
Attenuation
OUT Settling Time
OUT Voltage Range
SET Voltage Drift
SDA, SCL, SCL_S, WPn Input
Logic High
SDA, SCL, SCL_S, WPn Input
Logic Low
SDA, SCL, SCL_S, WPn
Hysteresis
AVDD to
SET
OUT
ST
V
OUT
SET
VD
VIH
VIL
(Note 3)
to ±0.5 LSB Error Band (Note 3)
(Note 3)
25 to 55
Full
Full
(Note 3)
Full
4
FN6123.3
September 7, 2010
ISL45045
Electrical Specifications
Test Conditions: V
DD
= 3V, AVDD = 10V, OUT = 5V, R
SET
= 24.9kΩ; Unless Otherwise Specified.
Typicals are at T
A
= +25°C
(Continued)
SYMBOL
IL
WPN
VOH
S
VOL
S
VOH
WPP
VOL
WPP
t
DWPP
@ 3mA
@ 3mA
@ 3mA
@ 3mA
TEST CONDITIONS
TEMP
(°C)
Full
Full
Full
Full
Full
Full
Full
t
S
Full
MIN
(Note 7)
15
0.4
-
VDD - 0.4
0.4
-
-
-
TYP
25
-
-
-
-
-
-
-
MAX
(Note 7)
35
-
0.4
-
-
100
75
60
UNITS
µA
V
V
V
V
ns
Ω
ns
PARAMETER
WPn IL
SDA, SCL Output Logic High
SDA, SCL Output Logic Low
WPp Output Logic High
WPp Output Logic Low
WPp Delay
SCL_S to SCL On Resistance
Delay From SCL_S to SCL
I
2
C
SCL Clock Frequency
I
2
C Clock High Time
I
2
C Clock Low Time
I
2
C Spike Rejection Filter Pulse
Width
I
2
C Data Set-up Time
I
2
C Data Hold Time
I
2
C SDA, SCL Input Rise Time
I
2
C SDA, SCL Input Fall Time
I
2
C Bus Free Time Between Stop
and Start
I
2
C Repeated Start Condition
Set-up
I
2
C Repeated Start Condition
Hold
I
2
C Stop Condition Set-up
I
2
C Bus Capacitive Load
Capacitance on SDA
Capacitance on SCL, SCL_S
F
SCL
t
SCH
t
SCL
t
DSP
t
SDS
t
SDH
t
ICR
t
ICF
t
BUF
t
STS
t
STH
t
SPS
Cb
C
SDA
C
S
WPn = 0
WPn = 1
Dependent on Load (Note 6)
(Note 6)
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
0
0.6
1.3
0
100
0
-
-
1.3
0.6
0.6
0.6
-
-
-
-
-
-
-
-
-
-
20 + 0.1*Cb
20 + 0.1*Cb
-
-
-
-
-
-
-
-
-
400
-
-
50
-
900
1000
300
-
-
-
-
400
10
10
22
100
kHz
µs
µs
ns
ns
ns
ns
ns
µs
µs
µs
µs
pF
pF
pF
pF
ms
Write Cycle Time
NOTES:
2. Tested at AVDD = 18V.
t
W
Full
-
3. Simulated and Determined via Design and NOT Directly Tested.
4. Simulated Maximum Current Draw when Programming EEPROM is 23mA, should be considered when designing Power Supply.
6. Simulated and Designed According to I
2
C Specifications.
5. A Typical Current of 20µA is Calculated using the AVDD = 10V and R
SET
= 24.9kΩ. The maximum suggested SET Current should be 120µA.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
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